49 lines
1.5 KiB
Verilog
49 lines
1.5 KiB
Verilog
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// Map the endpoint dest part of the SID in the CVITA header to a destination
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// This destination (o_tdest) signal will be valid with o_tdata
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// This only works with VALID CVITA frames
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module cvita_dest_lookup
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#(
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parameter DEST_WIDTH = 4
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)
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(
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input clk, input rst,
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input set_stb, input [7:0] set_addr, input [DEST_WIDTH-1:0] set_data,
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input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
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output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
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output [DEST_WIDTH-1:0] o_tdest
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);
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reg [7:0] endpoint;
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ram_2port #(.DWIDTH(DEST_WIDTH), .AWIDTH(8)) dest_lut
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(
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.clka(clk), .ena(1'b1), .wea(set_stb), .addra(set_addr), .dia(set_data), .doa(),
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.clkb(clk), .enb(1'b1), .web(1'b0), .addrb(endpoint), .dib(8'hff), .dob(o_tdest)
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);
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reg forward;
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reg [1:0] count;
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always @(posedge clk) begin
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if (rst) begin
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forward <= 1'b0;
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count <= 2'b0;
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end
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else if (forward == 1'b0 && i_tvalid) begin
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if (count == 2'b11) forward <= 1'b1;
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endpoint <= i_tdata[23:16];
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count <= count + 1'b1;
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end
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else if (forward == 1'b1 && i_tvalid && i_tready && i_tlast) begin
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forward <= 1'b0;
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count <= 2'b0;
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end
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end
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assign o_tdata = i_tdata;
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assign o_tlast = i_tlast;
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assign o_tvalid = i_tvalid && forward;
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assign i_tready = o_tready && forward;
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endmodule // cvita_dest_lookup
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