89 lines
2.2 KiB
Verilog
89 lines
2.2 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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// Special case SIZE <= 5 uses a short fifo
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module axi_fifo_2clk
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#(parameter WIDTH=69, SIZE=9)
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(input reset,
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input i_aclk,
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input [WIDTH-1:0] i_tdata,
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input i_tvalid,
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output i_tready,
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input o_aclk,
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output [WIDTH-1:0] o_tdata,
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output o_tvalid,
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input o_tready);
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wire write, read, empty, full;
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assign i_tready = ~full;
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assign write = i_tvalid & i_tready;
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wire [71:0] tdata_int;
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wire tvalid_int, tready_int;
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assign tvalid_int = ~empty;
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assign read = tvalid_int & tready_int;
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wire [71:0] wr_data;
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assign wr_data[WIDTH-1:0] = i_tdata;
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wire [71:0] rd_data;
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assign tdata_int = rd_data[WIDTH-1:0];
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generate
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if(WIDTH<72) begin
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assign wr_data[71:WIDTH] = 0;
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end
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endgenerate
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generate
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if(SIZE<=5)
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fifo_short_2clk fifo_short_2clk
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(.rst(reset),
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.wr_clk(i_aclk),
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.din(wr_data), // input [71 : 0] din
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.wr_en(write), // input wr_en
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.full(full), // output full
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.wr_data_count(), // output [9 : 0] wr_data_count
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.rd_clk(o_aclk), // input rd_clk
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.dout(rd_data), // output [71 : 0] dout
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.rd_en(read), // input rd_en
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.empty(empty), // output empty
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.rd_data_count() // output [9 : 0] rd_data_count
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);
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else
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fifo_4k_2clk fifo_4k_2clk
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(.rst(reset),
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.wr_clk(i_aclk),
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.din(wr_data), // input [71 : 0] din
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.wr_en(write), // input wr_en
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.full(full), // output full
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.wr_data_count(), // output [9 : 0] wr_data_count
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.rd_clk(o_aclk), // input rd_clk
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.dout(rd_data), // output [71 : 0] dout
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.rd_en(read), // input rd_en
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.empty(empty), // output empty
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.rd_data_count() // output [9 : 0] rd_data_count
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);
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endgenerate
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generate
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if(SIZE>9)
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axi_fifo #(.WIDTH(WIDTH), .SIZE(SIZE)) fifo_1clk
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(.clk(o_aclk), .reset(reset), .clear(1'b0),
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.i_tdata(tdata_int), .i_tvalid(tvalid_int), .i_tready(tready_int),
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.o_tdata(o_tdata), .o_tvalid(o_tvalid), .o_tready(o_tready),
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.space(), .occupied());
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else
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begin
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assign o_tdata = tdata_int;
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assign o_tvalid = tvalid_int;
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assign tready_int = o_tready;
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end
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endgenerate
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endmodule // axi_fifo_2clk
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