35 lines
657 B
Verilog
35 lines
657 B
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2008 Matt Ettus
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//
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//
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// Clipping "macro", keeps the bottom bits
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module clip_reg
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#(parameter bits_in=0,
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parameter bits_out=0,
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parameter STROBED=1'b0)
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(input clk,
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input [bits_in-1:0] in,
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output reg [bits_out-1:0] out,
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input strobe_in,
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output reg strobe_out);
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wire [bits_out-1:0] temp;
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clip #(.bits_in(bits_in),.bits_out(bits_out)) clip (.in(in),.out(temp));
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always @(posedge clk)
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strobe_out <= strobe_in;
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always @(posedge clk)
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if(strobe_in | ~STROBED)
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out <= temp;
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endmodule // clip_reg
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