27 lines
1.0 KiB
Verilog
27 lines
1.0 KiB
Verilog
//
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// Copyright 2011-2012 Ettus Research LLC
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//
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// This module takes the settings bus on one clock domain and crosses it over to another domain
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// Typically it will be used with the input settings bus on the wishbone clock, and either
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// the system or dsp clock on the output side
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module settings_bus_crossclock
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#(parameter FLOW_CTRL=0, parameter AWIDTH=8, parameter DWIDTH=32)
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(input clk_i, input rst_i, input set_stb_i, input [AWIDTH-1:0] set_addr_i, input [DWIDTH-1:0] set_data_i,
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input clk_o, input rst_o, output set_stb_o, output [AWIDTH-1:0] set_addr_o, output [DWIDTH-1:0] set_data_o, input blocked);
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wire nfull, nempty;
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axi_fifo_2clk #(.WIDTH(AWIDTH + DWIDTH), .SIZE(0)) settings_fifo
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(.reset(rst_i),
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.i_aclk(clk_i), .i_tdata({set_addr_i,set_data_i}), .i_tvalid(set_stb_i), .i_tready(nfull),
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.o_aclk(clk_o), .o_tdata({set_addr_o,set_data_o}), .o_tready(set_stb_o), .o_tvalid(nempty));
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assign set_stb_o = nempty & (~blocked | ~FLOW_CTRL);
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endmodule // settings_bus_crossclock
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