41 lines
774 B
Verilog
41 lines
774 B
Verilog
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// Copyright 2014 Ettus Research LLC
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module axi_chdr_header_trigger
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#(
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parameter WIDTH=64,
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parameter SID=0
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)
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(input clk, input reset, input clear,
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input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, input i_tready,
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output trigger
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);
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reg state;
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localparam IDLE = 0;
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localparam RUN = 1;
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always @(posedge clk)
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if(reset | clear)
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state <= IDLE;
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else
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case (state)
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IDLE :
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if(i_tvalid && i_tready)
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state <= RUN;
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RUN :
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if(i_tready && i_tvalid && i_tlast)
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state <= IDLE;
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default :
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state <= IDLE;
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endcase // case (state)
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assign trigger = i_tvalid && i_tready && (state == IDLE) && (i_tdata[15:0] != SID);
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endmodule // axi_chdr_header_trigger
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