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Wade Fife ba66b26dc5 fpga: e320: Improve timing on LVDS interface 
Original-commit: c6578eda2ba482b87583ebd989cdf5cbd5c3f672
2020-12-11 07:41:13 -06:00
..
dts
e320: Swap out liberio for internal Ethernet
2020-07-16 10:00:12 -05:00
ip
fpga: e320: Update AXI interconnect address range
2020-08-28 15:07:38 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_e320.tcl
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2020-01-28 09:35:36 -08:00
dev_config.json
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2020-01-28 09:35:36 -08:00
e320_1ge.xdc
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2020-01-28 09:35:36 -08:00
e320_10ge_port0.xdc
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2020-01-28 09:35:36 -08:00
e320_10ge.xdc
Merge FPGA repository back into UHD repository
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e320_aurora.xdc
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2020-01-28 09:35:36 -08:00
e320_clocking.v
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2020-01-28 09:35:36 -08:00
e320_core.v
fpga: Update DRAM IO signatures
2020-09-03 15:26:33 -05:00
e320_dram.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e320_rfnoc_image_core.v
E320: Revert addition of Replay block
2020-09-04 15:45:51 -07:00
e320_rfnoc_image_core.yml
E320: Revert addition of Replay block
2020-09-04 15:45:51 -07:00
e320_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
e320.v
fpga: e320: Improve timing on LVDS interface
2020-12-11 07:41:13 -06:00
Makefile
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.e320.inc
E320: Revert addition of Replay block
2020-09-04 15:45:51 -07:00
mb_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mb_timing.xdc
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2020-01-28 09:35:36 -08:00
n3xx_mgt_io_core.v
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2020-01-28 09:35:36 -08:00
n3xx_sfp_wrapper.v
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setupenv.sh
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2020-01-28 09:35:36 -08:00