Max Köhler
ec70691e84
The clock crossing of the ctrlport used FIFOs to transfer requests and responses between clock domains. This commit adds a handshake based on the pulse synchronizer to reduce the resource usage for ctrlport clock domain crossing. Data is stored in a single register while the pulse synchronizer handles the signaling of valid flags. Original-commit: 2c2bb3a0b7269dcbd8b5933ce1c0c29ca17f599d
185 lines
6.0 KiB
Verilog
185 lines
6.0 KiB
Verilog
//
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// Copyright 2019 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_clk_cross
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//
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// Description:
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//
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// Crosses a CTRL Port request and response between two clock domains.
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//
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module ctrlport_clk_cross (
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input wire rst, // Can be either clock domain, but must be glitch-free
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//---------------------------------------------------------------------------
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// Input Clock Domain (Slave Interface)
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//---------------------------------------------------------------------------
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input wire s_ctrlport_clk,
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [ 9:0] s_ctrlport_req_portid,
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input wire [15:0] s_ctrlport_req_rem_epid,
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input wire [ 9:0] s_ctrlport_req_rem_portid,
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input wire [31:0] s_ctrlport_req_data,
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input wire [ 3:0] s_ctrlport_req_byte_en,
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input wire s_ctrlport_req_has_time,
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input wire [63:0] s_ctrlport_req_time,
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output wire s_ctrlport_resp_ack,
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output wire [ 1:0] s_ctrlport_resp_status,
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output wire [31:0] s_ctrlport_resp_data,
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//---------------------------------------------------------------------------
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// Output Clock Domain (Master Interface)
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//---------------------------------------------------------------------------
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input wire m_ctrlport_clk,
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output wire m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [19:0] m_ctrlport_req_addr,
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output wire [ 9:0] m_ctrlport_req_portid,
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output wire [15:0] m_ctrlport_req_rem_epid,
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output wire [ 9:0] m_ctrlport_req_rem_portid,
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output wire [31:0] m_ctrlport_req_data,
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output wire [ 3:0] m_ctrlport_req_byte_en,
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output wire m_ctrlport_req_has_time,
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output wire [63:0] m_ctrlport_req_time,
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data
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);
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//---------------------------------------------------------------------------
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// Reset sync to both clock domains
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//---------------------------------------------------------------------------
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wire m_rst, s_rst;
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reset_sync master_reset_sync_inst (
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.clk(m_ctrlport_clk), .reset_in(rst), .reset_out(m_rst)
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);
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reset_sync slave_reset_sync_inst (
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.clk(s_ctrlport_clk), .reset_in(rst), .reset_out(s_rst)
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);
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//---------------------------------------------------------------------------
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// Slave to Master Clock Crossing (Request)
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//---------------------------------------------------------------------------
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localparam REQ_W =
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1 + // ctrlport_req_wr
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1 + // ctrlport_req_rd
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20 + // ctrlport_req_addr
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10 + // ctrlport_req_portid
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16 + // ctrlport_req_rem_epid
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10 + // ctrlport_req_rem_portid
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32 + // ctrlport_req_data
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4 + // ctrlport_req_byte_en
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1 + // ctrlport_req_has_time
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64; // ctrlport_req_time
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wire [ REQ_W-1:0] s_req_flat;
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wire [ REQ_W-1:0] m_req_flat;
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wire m_req_flat_valid;
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wire m_ctrlport_req_wr_tmp;
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wire m_ctrlport_req_rd_tmp;
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assign s_req_flat = {
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s_ctrlport_req_wr,
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s_ctrlport_req_rd,
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s_ctrlport_req_addr,
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s_ctrlport_req_portid,
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s_ctrlport_req_rem_epid,
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s_ctrlport_req_rem_portid,
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s_ctrlport_req_data,
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s_ctrlport_req_byte_en,
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s_ctrlport_req_has_time,
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s_ctrlport_req_time
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};
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// Busy flag can be ignored as the response handshake takes at least the same
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// amount of cycles to transfer the response as this handshake instance needs
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// to release the busy flag as they are configured with the same amount of
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// synchronization stages. Furthermore the ctrlport protocol just allows for
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// one transaction to be active at the same time. A request can only be issued
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// once the response is provided.
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handshake #(
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.WIDTH(REQ_W)
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) req_handshake_inst (
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.clk_a(s_ctrlport_clk),
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.rst_a(s_rst),
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.valid_a((s_ctrlport_req_wr | s_ctrlport_req_rd) & ~s_rst),
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.data_a(s_req_flat),
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.busy_a(),
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.clk_b(m_ctrlport_clk),
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.valid_b(m_req_flat_valid),
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.data_b(m_req_flat)
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);
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assign {
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m_ctrlport_req_wr_tmp,
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m_ctrlport_req_rd_tmp,
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m_ctrlport_req_addr,
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m_ctrlport_req_portid,
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m_ctrlport_req_rem_epid,
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m_ctrlport_req_rem_portid,
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m_ctrlport_req_data,
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m_ctrlport_req_byte_en,
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m_ctrlport_req_has_time,
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m_ctrlport_req_time
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} = m_req_flat;
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assign m_ctrlport_req_wr = m_ctrlport_req_wr_tmp & m_req_flat_valid & ~m_rst;
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assign m_ctrlport_req_rd = m_ctrlport_req_rd_tmp & m_req_flat_valid & ~m_rst;
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//---------------------------------------------------------------------------
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// Master to Slave Clock Crossing (Response)
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//---------------------------------------------------------------------------
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localparam RESP_W =
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1 + // ctrlport_resp_ack,
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2 + // ctrlport_resp_status,
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32; // ctrlport_resp_data
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wire [RESP_W-1:0] m_resp_flat;
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wire [RESP_W-1:0] s_resp_flat;
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wire s_resp_flat_valid;
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wire s_ctrlport_resp_ack_tmp;
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assign m_resp_flat = {
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m_ctrlport_resp_ack,
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m_ctrlport_resp_status,
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m_ctrlport_resp_data
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};
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// Busy flag can be ignored as the request handshake takes at least the same
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// amount of cycles to transfer the request as this handshake instance needs
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// to release the busy flag as they are configured with the same amount of
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// synchronization stages. Furthermore the ctrlport protocol just allows for
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// one transaction to be active at the same time. A response can only be
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// issued once the request is available.
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handshake #(
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.WIDTH(RESP_W)
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) resp_handshake_inst (
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.clk_a(m_ctrlport_clk),
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.rst_a(m_rst),
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.valid_a(m_ctrlport_resp_ack & ~m_rst),
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.data_a(m_resp_flat),
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.busy_a(),
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.clk_b(s_ctrlport_clk),
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.valid_b(s_resp_flat_valid),
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.data_b(s_resp_flat)
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);
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assign {
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s_ctrlport_resp_ack_tmp,
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s_ctrlport_resp_status,
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s_ctrlport_resp_data
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} = s_resp_flat;
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assign s_ctrlport_resp_ack = s_ctrlport_resp_ack_tmp & s_resp_flat_valid & ~s_rst;
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endmodule
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