271 lines
10 KiB
Verilog
271 lines
10 KiB
Verilog
//
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// Copyright 2019 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_combiner
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//
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// Description:
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//
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// This block is an arbiter that merges control-port interfaces. This block is
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// used when you have multiple control-port masters that need to access a
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// single slave. For example, a NoC block with multiple submodules that each
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// need to read and/or write registers outside of themselves.
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//
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// This module combines the control-port requests from multiple masters into a
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// single request for one slave. Simultaneous requests are handled in the order
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// specified by PRIORITY. The responding ACK is routed back to the requester.
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//
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// The module has been designed so that the latency through it is always the
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// same when PRIORITY=1 and there is no contention, so that it can be used in
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// applications where deterministic behavior is desired.
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//
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// Parameters:
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//
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// NUM_MASTERS : The number of control-port masters to connect to a single
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// control-port slave.
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// PRIORITY : Use PRIORITY = 0 for round robin arbitration, PRIORITY = 1
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// for priority arbitration (lowest number port serviced first).
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//
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module ctrlport_combiner #(
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parameter NUM_MASTERS = 2,
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parameter PRIORITY = 0
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) (
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// Requests from multiple masters
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input wire [ NUM_MASTERS-1:0] s_ctrlport_req_wr,
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input wire [ NUM_MASTERS-1:0] s_ctrlport_req_rd,
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input wire [20*NUM_MASTERS-1:0] s_ctrlport_req_addr,
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input wire [10*NUM_MASTERS-1:0] s_ctrlport_req_portid,
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input wire [16*NUM_MASTERS-1:0] s_ctrlport_req_rem_epid,
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input wire [10*NUM_MASTERS-1:0] s_ctrlport_req_rem_portid,
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input wire [32*NUM_MASTERS-1:0] s_ctrlport_req_data,
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input wire [ 4*NUM_MASTERS-1:0] s_ctrlport_req_byte_en,
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input wire [ NUM_MASTERS-1:0] s_ctrlport_req_has_time,
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input wire [64*NUM_MASTERS-1:0] s_ctrlport_req_time,
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// Responses to multiple masters
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output reg [ NUM_MASTERS-1:0] s_ctrlport_resp_ack,
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output reg [ 2*NUM_MASTERS-1:0] s_ctrlport_resp_status,
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output reg [32*NUM_MASTERS-1:0] s_ctrlport_resp_data,
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// Request to a single slave
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output reg m_ctrlport_req_wr,
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output reg m_ctrlport_req_rd,
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output reg [19:0] m_ctrlport_req_addr,
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output reg [ 9:0] m_ctrlport_req_portid,
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output reg [15:0] m_ctrlport_req_rem_epid,
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output reg [ 9:0] m_ctrlport_req_rem_portid,
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output reg [31:0] m_ctrlport_req_data,
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output reg [ 3:0] m_ctrlport_req_byte_en,
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output reg m_ctrlport_req_has_time,
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output reg [63:0] m_ctrlport_req_time,
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// Response from a single slave
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data
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);
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reg [$clog2(NUM_MASTERS)-1:0] slave_sel = 0; // Tracks which slave port is
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// currently being serviced.
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reg req_load_output = 1'b0;
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// Helper function to convert one hot vector to binary index
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// (LSB = index 0)
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function integer one_hot_to_binary(input [NUM_MASTERS-1:0] one_hot_vec);
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integer i, total;
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begin
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total = 0;
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for (i = 0; i <= NUM_MASTERS-1; i = i + 1) begin
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if (one_hot_vec[i]) begin
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total = total + i;
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end
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end
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one_hot_to_binary = total;
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end
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endfunction
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//---------------------------------------------------------------------------
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// Input Registers
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//---------------------------------------------------------------------------
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//
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// Latch each request until it can be serviced. Only one request per slave
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// can be in progress at a time.
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//
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//---------------------------------------------------------------------------
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reg [ NUM_MASTERS-1:0] req_valid = 0;
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reg [ NUM_MASTERS-1:0] req_wr;
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reg [ NUM_MASTERS-1:0] req_rd;
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reg [20*NUM_MASTERS-1:0] req_addr;
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reg [10*NUM_MASTERS-1:0] req_portid;
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reg [16*NUM_MASTERS-1:0] req_rem_epid;
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reg [10*NUM_MASTERS-1:0] req_rem_portid;
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reg [32*NUM_MASTERS-1:0] req_data;
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reg [ 4*NUM_MASTERS-1:0] req_byte_en;
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reg [ NUM_MASTERS-1:0] req_has_time;
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reg [64*NUM_MASTERS-1:0] req_time;
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always @(posedge ctrlport_clk) begin : input_buffer_block
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integer i;
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if (ctrlport_rst) begin
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req_valid <= 0;
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end else begin : input_reg_gen
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for (i = 0; i < NUM_MASTERS; i = i + 1) begin
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if (s_ctrlport_req_wr[i] | s_ctrlport_req_rd[i]) begin
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// Mark this slave's request valid and save the request information
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req_valid[i] <= 1'b1;
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end
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end
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// Clear the active request when it gets output
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if (req_load_output) begin
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req_valid[slave_sel] <= 1'b0;
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end
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end
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// Buffer request information without reset
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for (i = 0; i < NUM_MASTERS; i = i + 1) begin
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if (s_ctrlport_req_wr[i] | s_ctrlport_req_rd[i]) begin
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req_wr[i] <= s_ctrlport_req_wr[i];
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req_rd[i] <= s_ctrlport_req_rd[i];
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req_addr[20*i+:20] <= s_ctrlport_req_addr[20*i+:20];
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req_portid[10*i+:10] <= s_ctrlport_req_portid[10*i+:10];
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req_rem_epid[16*i+:16] <= s_ctrlport_req_rem_epid[16*i+:16];
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req_rem_portid[10*i+:10] <= s_ctrlport_req_rem_portid[10*i+:10];
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req_data[32*i+:32] <= s_ctrlport_req_data[32*i+:32];
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req_byte_en[4*i+:4] <= s_ctrlport_req_byte_en[4*i+:4];
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req_has_time[i] <= s_ctrlport_req_has_time[i];
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req_time[64*i+:64] <= s_ctrlport_req_time[64*i+:64];
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end
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end
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end
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//---------------------------------------------------------------------------
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// Arbitration State Machine
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//---------------------------------------------------------------------------
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//
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// This state machine tracks which slave port is being serviced and which to
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// service next. This is done using a counter that simply checks each port in
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// sequential order and then stops when it finds one that has a valid request.
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//
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//---------------------------------------------------------------------------
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reg req_active = 0; // Indicates if there's a request being serviced
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wire [NUM_MASTERS-1:0] next_slave_one_hot; // one hot for next active request
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// (used for PRIORITY = 1)
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generate
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genvar i;
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for (i = 0; i < NUM_MASTERS; i = i+1) begin : gen_next_slave_one_hot
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if (i == 0) begin
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assign next_slave_one_hot[i] = req_valid[i];
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end else begin
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assign next_slave_one_hot[i] = req_valid[i] & ~next_slave_one_hot[i-1];
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end
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end
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endgenerate
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always @(posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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slave_sel <= 0;
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req_active <= 1'b0;
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req_load_output <= 1'b0;
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end else begin
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req_load_output <= 1'b0;
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if (req_active) begin
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// Wait until we get the response before we allow another request
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if (m_ctrlport_resp_ack) begin
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req_active <= 1'b0;
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// Go to next slave immediately
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if(PRIORITY == 1)
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slave_sel <= one_hot_to_binary(next_slave_one_hot);
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// Round robin - Go to the next slave so we don't service the same
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// slave again
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else if(slave_sel == NUM_MASTERS-1)
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slave_sel <= 0;
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else
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slave_sel <= slave_sel + 1;
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end
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end else begin
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// No active request in progress, so check if there's a new request on
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// the selected slave.
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if (req_valid[slave_sel]) begin
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req_active <= 1'b1;
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req_load_output <= 1'b1;
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end else begin
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// Go to next slave immediately
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if(PRIORITY == 1)
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slave_sel <= one_hot_to_binary(next_slave_one_hot);
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// Round robin - Nothing from this slave, so move to the next slave.
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else if (slave_sel == NUM_MASTERS-1)
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slave_sel <= 0;
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else
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slave_sel <= slave_sel + 1;
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end
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end
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end
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end
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//---------------------------------------------------------------------------
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// Output Register
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//---------------------------------------------------------------------------
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//
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// Here we load the active request for a single clock cycle and demultiplex
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// the response back to the requesting master.
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//
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//---------------------------------------------------------------------------
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always @(posedge ctrlport_clk) begin : output_reg_gen
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integer i;
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// ---------- Request --------------
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// Load the active request
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if (req_load_output) begin
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m_ctrlport_req_wr <= req_wr [slave_sel];
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m_ctrlport_req_rd <= req_rd [slave_sel];
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m_ctrlport_req_addr <= req_addr [20*slave_sel +: 20];
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m_ctrlport_req_portid <= req_portid [10*slave_sel +: 10];
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m_ctrlport_req_rem_epid <= req_rem_epid [16*slave_sel +: 16];
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m_ctrlport_req_rem_portid <= req_rem_portid[10*slave_sel +: 10];
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m_ctrlport_req_data <= req_data [32*slave_sel +: 32];
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m_ctrlport_req_byte_en <= req_byte_en [ 4*slave_sel +: 4];
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m_ctrlport_req_has_time <= req_has_time [slave_sel];
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m_ctrlport_req_time <= req_time [64*slave_sel +: 64];
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end else begin
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m_ctrlport_req_wr <= 1'b0;
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m_ctrlport_req_rd <= 1'b0;
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end
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if (ctrlport_rst) begin
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m_ctrlport_req_wr <= 1'b0;
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m_ctrlport_req_rd <= 1'b0;
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end
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// ---------- Response --------------
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// Output any response to the master that made the request
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for (i = 0; i < NUM_MASTERS; i = i + 1) begin
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// Give the response data to all the slaves (no demux, to save logic)
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s_ctrlport_resp_status[2*i +: 2] <= m_ctrlport_resp_status;
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s_ctrlport_resp_data[32*i +: 32] <= m_ctrlport_resp_data;
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// Give the ack only to the master that made the request (use a demux)
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if (ctrlport_rst) begin
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s_ctrlport_resp_ack[i] <= 1'b0;
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end else if (i == slave_sel && m_ctrlport_resp_ack) begin
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s_ctrlport_resp_ack[i] <= 1'b1;
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end else begin
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s_ctrlport_resp_ack[i] <= 1'b0;
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end
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end
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end
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endmodule
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