99 lines
2.9 KiB
Systemverilog
99 lines
2.9 KiB
Systemverilog
//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axi4s_packet_gate
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//
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// Description:
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// System Verilog wrapper for axi_gate_packet that accepts
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// a AxiStreamIfc with slave_user/master_uer interface.
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//
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// Parameters:
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// TDATA - store tData if 1
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// TUSER - store tUser if 1
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// SIZE - 2**SIZE words are stored
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// USE_AS_BUFF - Allow the packet gate to be used as a buffer (uses more RAM)
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// MIN_PKT_SIZE - log2 of minimum valid packet size (rounded down, used to
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// reduce addr fifo size)
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module axi4s_packet_gate #(
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bit TDATA = 1,
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bit TUSER = 1,
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int SIZE = 10,
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bit USE_AS_BUFF = 1,
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int MIN_PKT_SIZE= 1
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) (
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input logic clear=1'b0,
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input logic error=1'b0,
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interface.slave i, // AxiStreamIf or AxiStreamPacketIf
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interface.master o // AxiStreamIf or AxiStreamPacketIf
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);
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`include "axi4s.vh"
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// Parameter Checks
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initial begin
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assert (i.DATA_WIDTH == o.DATA_WIDTH) else
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$fatal(1, "DATA_WIDTH mismatch");
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assert (i.USER_WIDTH == o.USER_WIDTH) else
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$fatal(1, "USER_WIDTH mismatch");
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assert (i.TDATA == o.TDATA) else
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$fatal(1, "TDATA present mismatch");
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assert (i.TUSER == o.TUSER) else
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$fatal(1, "TUSER present mismatch");
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assert (i.TKEEP == o.TKEEP) else
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$fatal(1, "TKEEP present mismatch");
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assert (i.TLAST == 1) else
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$fatal(1, "i.TLAST not present");
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assert (o.TLAST == 1) else
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$fatal(1, "o.TLAST not present");
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end
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localparam WIDTH = i.DWIDTH + i.UWIDTH + i.KWIDTH;
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AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH),
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.TDATA(i.TDATA),.TKEEP(i.TKEEP),.TUSER(i.TUSER),.TLAST(i.TLAST),
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.MAX_PACKET_BYTES(i.MAX_PACKET_BYTES))
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s0(i.clk,i.rst);
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AxiStreamPacketIf #(.DATA_WIDTH(i.DATA_WIDTH),.USER_WIDTH(i.USER_WIDTH),
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.TDATA(i.TDATA),.TKEEP(i.TKEEP),.TUSER(i.TUSER),.TLAST(i.TLAST),
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.MAX_PACKET_BYTES(i.MAX_PACKET_BYTES))
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s1(i.clk,i.rst);
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// move from AxiStreamIfc to AxiStreamPacketIf
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always_comb begin
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`AXI4S_ASSIGN(s0,i)
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end
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// move from AxiStreamPacketIf to AxiStreamIfc
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always_comb begin
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`AXI4S_ASSIGN(o,s1)
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end
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logic [WIDTH-1:0] s0_data;
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logic [WIDTH-1:0] s1_data;
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always_comb s0_data = s0.pack(.INC_LAST(0));
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always_comb s1.unpack(s1_data,.INC_LAST(0));
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logic s0_ready, s1_valid, s1_last;
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always_comb s0.tready = s0_ready;
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always_comb s1.tvalid = s1_valid;
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always_comb s1.tlast = s1_last;
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axi_packet_gate #(
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.WIDTH(WIDTH),.SIZE(SIZE), .USE_AS_BUFF(USE_AS_BUFF), .MIN_PKT_SIZE(MIN_PKT_SIZE)
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) axi_packet_gate_i (
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.clk(s0.clk), .reset(s0.rst), .clear(clear),
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.i_terror(error),
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.i_tdata(s0_data),
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.i_tvalid(s0.tvalid),
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.i_tready(s0_ready),
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.i_tlast(s0.tlast),
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.o_tdata(s1_data),
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.o_tvalid(s1_valid),
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.o_tready(s1.tready),
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.o_tlast(s1_last)
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);
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endmodule : axi4s_packet_gate
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