160 lines
4.8 KiB
Verilog
160 lines
4.8 KiB
Verilog
//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: sine_tone
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//
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// Description:
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//
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// Sine tone generator. This block uses the Xilinx CORDIC IP configured to
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// perform the rotate function in units of scaled radians. See the CORDIC IP
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// Product Guide (PG105) for details.
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//
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// The SR_PHASE_INC register controls the phase increment, in scaled
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// radians, for the sine waveform generator. It is a 16-bit signed
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// fixed-point phase value with 3 integer bits and 13 fractional bits. This
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// is the amount by which REG_CARTESIAN is rotated each clock cycle. In
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// other words, it controls the rate of rotation, or the frequency, of the
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// sine wave. In scaled radians, the phase value range -1 to +1 corresponds
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// to -Pi to Pi in radians.
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//
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// The SR_CARTESIAN register sets the sets the (X,Y) Cartesian coordinate
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// that will be rotated to generate the sine output. Both X and Y are 16-bit
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// signed fixed-point values with 2 integer bits and 14 fractional bits. Y
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// is in the upper 16-bits and X is in the lower 16-bits.
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//
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// In addition to rotation, the SR_CARTESIAN input vector is also scaled by
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// a "CORDIC scale factor" that equals about 1.1644 (that is, the product of
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// sqrt(1 + 2^(-2i)) for i = 1 to n, where n = 14, the number of fractional
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// bits).
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//
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// Parameters:
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//
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// SR_PHASE_INC_ADDR : The address to use for SR_PHASE_INC.
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// SR_CARTESIAN_ADDR : The address to use for SR_CARTESIAN.
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//
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module sine_tone #(
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parameter WIDTH = 32,
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parameter SR_PHASE_INC_ADDR = 129,
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parameter SR_CARTESIAN_ADDR = 130
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) (
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input clk,
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input reset,
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input clear,
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input enable,
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// Settings bus
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input set_stb,
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input [WIDTH-1:0] set_data,
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input [ 7:0] set_addr,
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// Output sinusoid
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output [WIDTH-1:0] o_tdata,
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output o_tlast,
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output o_tvalid,
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input o_tready
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);
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wire [15:0] phase_in_tdata;
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wire phase_in_tlast;
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wire phase_in_tvalid;
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wire phase_in_tready;
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wire [15:0] phase_out_tdata;
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wire phase_out_tlast;
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wire phase_out_tvalid;
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wire phase_out_tready;
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wire [WIDTH-1:0] cartesian_tdata;
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wire cartesian_tlast;
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wire cartesian_tvalid;
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wire cartesian_tready;
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wire [WIDTH-1:0] sine_out_tdata;
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wire sine_out_tlast;
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wire sine_out_tvalid;
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wire sine_out_tready;
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// AXI settings bus for phase values
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axi_setting_reg #(
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.ADDR (SR_PHASE_INC_ADDR),
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.AWIDTH (8),
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.WIDTH (16),
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.STROBE_LAST (1),
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.REPEATS (1)
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) set_phase_acc (
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.clk (clk),
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.reset (reset),
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.error_stb (),
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.set_stb (set_stb),
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.set_addr (set_addr),
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.set_data (set_data),
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.o_tdata (phase_in_tdata),
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.o_tlast (phase_in_tlast),
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.o_tvalid (phase_in_tvalid),
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.o_tready (phase_in_tready & enable)
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);
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// AXI settings bus for Cartesian values
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axi_setting_reg #(
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.ADDR (SR_CARTESIAN_ADDR),
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.AWIDTH (8),
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.WIDTH (32),
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.REPEATS (1)
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) set_axis_cartesian (
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.clk (clk),
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.reset (reset),
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.error_stb (),
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.set_stb (set_stb),
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.set_addr (set_addr),
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.set_data (set_data),
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.o_tdata (cartesian_tdata),
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.o_tlast (),
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.o_tvalid (cartesian_tvalid),
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.o_tready (cartesian_tready & enable)
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);
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assign cartesian_tlast = 1;
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// Phase accumulator
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phase_accum phase_acc (
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.clk (clk),
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.reset (reset),
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.clear (clear),
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.i_tdata (phase_in_tdata),
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.i_tlast (phase_in_tlast),
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.i_tvalid (1'b1),
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.i_tready (phase_in_tready),
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.o_tdata (phase_out_tdata),
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.o_tlast (phase_out_tlast),
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.o_tvalid (phase_out_tvalid),
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.o_tready (phase_out_tready & enable)
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);
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// CORDIC
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cordic_rotator cordic_inst (
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.aclk (clk),
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.aresetn (~(reset|clear)),
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.s_axis_phase_tdata (phase_out_tdata),
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.s_axis_phase_tvalid (phase_out_tvalid & cartesian_tvalid & enable),
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.s_axis_phase_tready (phase_out_tready),
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.s_axis_cartesian_tdata (cartesian_tdata),
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.s_axis_cartesian_tlast (cartesian_tlast),
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.s_axis_cartesian_tvalid (phase_out_tvalid & cartesian_tvalid & enable),
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.s_axis_cartesian_tready (cartesian_tready),
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.m_axis_dout_tdata (sine_out_tdata),
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.m_axis_dout_tlast (sine_out_tlast),
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.m_axis_dout_tvalid (sine_out_tvalid),
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.m_axis_dout_tready (sine_out_tready & enable)
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);
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assign o_tdata = sine_out_tdata;
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assign o_tlast = sine_out_tlast;
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assign o_tvalid = sine_out_tvalid;
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assign sine_out_tready = o_tready;
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endmodule // sine_tone
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