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Wade Fife 5a99bed5ee fpga: lib: Fix SWITCH_ON_LAST in axi_mux_select 
Thange allows the mux to switch cleanly between packets, if the mux
select input is changed while a packet is in flight.


Original-commit: cee09d96aee51795ba2c6578f75f25f30ea11548
2020-08-13 15:23:26 -05:00
..
axi_demux4.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_demux8.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_demux.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo16_to_fifo32.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo32_to_fifo16.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo32_to_fifo64.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo64_to_fifo32.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo_2clk.v
fpga: lib: add Intel MAX10 architecture for 2clk FIFO
2020-08-06 16:17:33 -05:00
axi_fifo_32_64_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo_bram.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo_cascade.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo_flop2.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo_flop.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo_short.v
fpga: lib: Fix comments and indentation in axi_fifo_short.v
2020-08-04 15:40:08 -05:00
axi_fifo_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_filter_mux4.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_loopback.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_mux4.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_mux8.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_mux_select.v
fpga: lib: Fix SWITCH_ON_LAST in axi_mux_select
2020-08-13 15:23:26 -05:00
axi_mux.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_packet_gate.v
fpga: lib: Fix axi_packet_gate RAM dib width
2020-06-29 13:41:15 -05:00
axis_fifo_monitor.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axis_strm_monitor.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
fifo64_to_axi4lite.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.srcs
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
shortfifo.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00