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Paul Butler ce701301d0 fpga: tools: Add support for .sdc in Vivado 
viv_utils.tcl will now read files with the .sdc suffix using the
read_xdc Vivado command. This is especially useful when I/O timing
constraints in the FPGA and CPLD need to depend on a common constant.


Original-commit: b47b1a467ee5796dbce359ff34c9d55a6acebc82
2020-04-02 08:13:35 -05:00
..
auto_inst_e310.yml
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
auto_inst_x310.yml
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
check_config.json
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
git-hash.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ise_jtag_program.sh
Merge FPGA repository back into UHD repository
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launch_vivado.py
Merge FPGA repository back into UHD repository
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launch_vivado.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
setupenv_base.sh
fpga: tools: Add default Vivado install location
2020-04-01 08:45:41 -05:00
shared-ip-loc-manage.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
uhd_image_builder_gui.py
Merge FPGA repository back into UHD repository
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uhd_image_builder.py
Merge FPGA repository back into UHD repository
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viv_check_syntax.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_gen_ip_makefile.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_gen_part_id.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_generate_bd.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_generate_hls_ip.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_generate_ip.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_hardware_utils.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_ip_utils.tcl
fpga: tools: Ignore BD layout info for TCL-based BD
2020-03-12 10:33:24 -05:00
viv_ip_xci_editor.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_sim_project.tcl
fpga: tools: Add modelsim to make sim targets
2020-03-20 10:34:59 -05:00
viv_strategies.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_synth.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_utils.tcl
fpga: tools: Add support for .sdc in Vivado
2020-04-02 08:13:35 -05:00
xil_bitfile_parser.py
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00