91 lines
2.7 KiB
Verilog
91 lines
2.7 KiB
Verilog
//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_to_regport
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//
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// Description:
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//
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// This is a bridge that converts a CtrlPort request to a RegPort request. No
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// address translation or filtering is performed. In the case where the
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// REG_AWIDTH and/or REG_DWIDTH parameters don't match the widths used by
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// CtrlPort, the address and data are simply resized according to Verilog
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// rules.
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//
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// Because RegPort doesn't acknowledge writes, this block will acknowledge
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// every write request. The designer must ensure that all requests are for
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// the address space behind this bridge or else they may get an unintended
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// write acknowledgment from this block.
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//
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// Parameters:
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//
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// REG_AWIDTH : Width of the RegPort address bus
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// REG_DWIDTH : Width of the RegPort data bugs
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module ctrlport_to_regport #(
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parameter REG_AWIDTH = 20,
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parameter REG_DWIDTH = 32
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) (
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input clk,
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input rst,
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input wire s_ctrlport_req_wr,
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input wire s_ctrlport_req_rd,
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input wire [19:0] s_ctrlport_req_addr,
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input wire [31:0] s_ctrlport_req_data,
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output reg s_ctrlport_resp_ack = 1'b0,
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output reg [31:0] s_ctrlport_resp_data = 'bX,
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output reg reg_wr_req = 1'b0,
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output reg [REG_AWIDTH-1:0] reg_wr_addr = 'bX,
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output reg [REG_DWIDTH-1:0] reg_wr_data = 'bX,
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output reg reg_rd_req = 1'b0,
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output reg [REG_AWIDTH-1:0] reg_rd_addr = 'bX,
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input wire reg_rd_resp,
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input wire [REG_DWIDTH-1:0] reg_rd_data
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);
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always @(posedge clk) begin
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if (rst) begin
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s_ctrlport_resp_ack <= 1'b0;
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s_ctrlport_resp_data <= 'bx;
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reg_wr_req <= 1'b0;
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reg_wr_addr <= 'bX;
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reg_wr_data <= 'bX;
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reg_rd_req <= 1'b0;
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reg_rd_addr <= 'bX;
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end else begin
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// Default assignments
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s_ctrlport_resp_ack <= 1'b0;
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reg_wr_req <= 1'b0;
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reg_rd_req <= 1'b0;
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// Translate write requests
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if (s_ctrlport_req_wr) begin
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reg_wr_req <= 1'b1;
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reg_wr_addr <= s_ctrlport_req_addr;
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reg_wr_data <= s_ctrlport_req_data;
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// RegPort has no write acknowledge, so we acknowledge every write
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s_ctrlport_resp_ack <= 1'b1;
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end
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// Translate read requests
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if (s_ctrlport_req_rd) begin
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reg_rd_req <= 1'b1;
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reg_rd_addr <= s_ctrlport_req_addr;
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end
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// Translate read responses
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if (reg_rd_resp) begin
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s_ctrlport_resp_ack <= 1'b1;
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s_ctrlport_resp_data <= reg_rd_data;
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end
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end
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end
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endmodule
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