307 lines
9.8 KiB
Systemverilog
307 lines
9.8 KiB
Systemverilog
//
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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// Module: eth_ipv4_interface
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//
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// Description:
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// Adapts from internal CHDR to UDP/IPV4 Ethernet packets.
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// Packets not specifically addressed to CHDR are routed
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// to the CPU
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//
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// Parameters:
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// - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>}
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// - CPU_FIFO_SIZE: Log2 of the FIFO depth (in bytes) for the CPU egress path
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// - CHDR_FIFO_SIZE: Log2 of the FIFO depth (in bytes) for the CHDR egress path
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// - RT_TBL_SIZE: Log2 of the depth of the return-address routing table
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// - NODE_INST: The node type to return for a node-info discovery
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// - DROP_UNKNOWN_MAC: Drop packets not addressed to us?
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// - DROP_MIN_PACKET: Drop packets smaller than 64 bytes?
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// - PREAMBLE_BYTES: Number of bytes of Preamble expected
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// - ADD_SOF: Add a SOF indication into the tuser field of e2c
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// - SYNC: Set if the CPU clock domain (c2e, e2c) is not the same as the
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// Ethernet clock domain (eth_rx, eth_tx).
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// - ENET_W: Width of the link to the Ethernet MAC
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// - CPU_W: Width of the CPU interface
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// - CHDR_W: Width of the CHDR interface
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//
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module eth_ipv4_interface #(
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logic [15:0] PROTOVER = {8'd1, 8'd0},
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int CPU_FIFO_SIZE = $clog2(8*1024),
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int CHDR_FIFO_SIZE = $clog2(8*1024),
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int NODE_INST = 0,
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int RT_TBL_SIZE = 6,
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int REG_AWIDTH = 14,
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int BASE = 0,
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bit DROP_UNKNOWN_MAC = 0,
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bit DROP_MIN_PACKET = 0,
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int PREAMBLE_BYTES = 6,
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bit ADD_SOF = 1,
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bit SYNC = 0,
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bit PAUSE_EN = 0,
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int ENET_W = 64,
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int CPU_W = 64,
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int CHDR_W = 64
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) (
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input logic bus_clk,
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input logic bus_rst,
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input logic [15:0] device_id,
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// Register port: Write port (domain: bus_clk)
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input logic reg_wr_req,
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input logic [REG_AWIDTH-1:0] reg_wr_addr,
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input logic [31:0] reg_wr_data,
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// Register port: Read port (domain: bus_clk)
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input logic reg_rd_req,
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input logic [REG_AWIDTH-1:0] reg_rd_addr,
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output logic reg_rd_resp,
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output logic [31:0] reg_rd_data,
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// Status ports (domain: bus_clk)
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output logic [47:0] my_mac,
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output logic [31:0] my_ip,
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output logic [15:0] my_udp_chdr_port,
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// Ethernet MAC (domain: eth_rx.clk)
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output logic eth_pause_req,
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AxiStreamIf.master eth_tx, // tUser = {1'b0,trailing bytes};
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AxiStreamIf.slave eth_rx, // tUser = {error,trailing bytes};
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// CHDR router interface (domain: eth_rx.clk)
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AxiStreamIf.master e2v, // tUser = {*not used*};
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AxiStreamIf.slave v2e, // tUser = {*not used*};
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// CPU DMA
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// (domain: e2c.clk if SYNC=0, else eth_rx.clk)
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AxiStreamIf.master e2c, // tUser = {sof,trailing bytes};
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// (domain: c2e.clk if SYNC=0, else eth_rx.clk)
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AxiStreamIf.slave c2e // tUser = {1'b0,trailing bytes};
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);
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localparam [47:0] DEFAULT_MAC_ADDR = {8'h00, 8'h80, 8'h2f, 8'h16, 8'hc5, 8'h2f};
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localparam [31:0] DEFAULT_IP_ADDR = {8'd192, 8'd168, 8'd10, 8'd2};
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localparam [31:0] DEFAULT_UDP_PORT = 16'd49153;
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localparam [15:0] DEFAULT_PAUSE_SET = 16'd00040;
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localparam [15:0] DEFAULT_PAUSE_CLEAR = 16'd00020;
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//---------------------------------------------------------
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// Registers
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//---------------------------------------------------------
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// Include for register offsets
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`include "eth_regs.vh"
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// Allocate one full page for M
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// mac_reg: MAC address for the dispatcher module. This value is used to
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// determine if the packet is meant for this device and should be consumed.
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//
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// ip_reg: IP address for the dispatcher module. This value is used to
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// determine if the packet is addressed to this device
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//
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// This module supports two destination ports.
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logic [47:0] mac_reg = DEFAULT_MAC_ADDR;
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logic [31:0] ip_reg = DEFAULT_IP_ADDR;
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logic [15:0] udp_port = DEFAULT_UDP_PORT;
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logic [47:0] bridge_mac_reg = DEFAULT_MAC_ADDR;
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logic [31:0] bridge_ip_reg = DEFAULT_IP_ADDR;
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logic [15:0] bridge_udp_port = DEFAULT_UDP_PORT;
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logic bridge_en;
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logic cpu_dropped;
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logic chdr_dropped;
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logic [31:0] chdr_drop_count = 0;
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logic [31:0] cpu_drop_count = 0;
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logic [15:0] my_pause_set = DEFAULT_PAUSE_SET;
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logic [15:0] my_pause_clear = DEFAULT_PAUSE_CLEAR;
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always_comb begin : bridge_mux
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my_mac = bridge_en ? bridge_mac_reg : mac_reg;
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my_ip = bridge_en ? bridge_ip_reg : ip_reg;
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my_udp_chdr_port = bridge_en ? bridge_udp_port : udp_port;
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end
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always_ff @(posedge bus_clk) begin : reg_wr_ff
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if (bus_rst) begin
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mac_reg <= DEFAULT_MAC_ADDR;
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ip_reg <= DEFAULT_IP_ADDR;
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udp_port <= DEFAULT_UDP_PORT;
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bridge_en <= 1'b0;
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bridge_mac_reg <= DEFAULT_MAC_ADDR;
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bridge_ip_reg <= DEFAULT_IP_ADDR;
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bridge_udp_port <= DEFAULT_UDP_PORT;
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my_pause_set <= DEFAULT_PAUSE_SET;
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my_pause_clear <= DEFAULT_PAUSE_CLEAR;
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end
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else begin
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if (reg_wr_req)
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case (reg_wr_addr)
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REG_MAC_LSB:
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mac_reg[31:0] <= reg_wr_data;
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REG_MAC_MSB:
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mac_reg[47:32] <= reg_wr_data[15:0];
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REG_IP:
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ip_reg <= reg_wr_data;
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REG_UDP:
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udp_port <= reg_wr_data[15:0];
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REG_BRIDGE_MAC_LSB:
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bridge_mac_reg[31:0] <= reg_wr_data;
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REG_BRIDGE_MAC_MSB:
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bridge_mac_reg[47:32] <= reg_wr_data[15:0];
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REG_BRIDGE_IP:
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bridge_ip_reg <= reg_wr_data;
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REG_BRIDGE_UDP:
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bridge_udp_port <= reg_wr_data[15:0];
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REG_BRIDGE_ENABLE:
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bridge_en <= reg_wr_data[0];
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REG_PAUSE:
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begin
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if (PAUSE_EN) begin
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my_pause_set <= reg_wr_data[15:0];
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my_pause_clear <= reg_wr_data[31:16];
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end
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end
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endcase
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end
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end
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always_ff @ (posedge bus_clk) begin : reg_rd_ff
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if (bus_rst) begin
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reg_rd_resp <= 1'b0;
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reg_rd_data <= 32'd0;
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chdr_drop_count <= 32'd0;
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cpu_drop_count <= 32'd0;
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end
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else begin
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if (chdr_dropped) begin
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chdr_drop_count <= chdr_drop_count+1;
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end
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if (cpu_dropped) begin
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cpu_drop_count <= cpu_drop_count+1;
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end
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if (reg_rd_req) begin
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// Assert read response one cycle after read request
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reg_rd_resp <= 1'b1;
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case (reg_rd_addr)
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REG_MAC_LSB:
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reg_rd_data <= mac_reg[31:0];
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REG_MAC_MSB:
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reg_rd_data <= {16'b0,mac_reg[47:32]};
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REG_IP:
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reg_rd_data <= ip_reg;
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REG_UDP:
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reg_rd_data <= {16'b0, udp_port};
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REG_BRIDGE_MAC_LSB:
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reg_rd_data <= bridge_mac_reg[31:0];
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REG_BRIDGE_MAC_MSB:
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reg_rd_data <= {16'b0,bridge_mac_reg[47:32]};
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REG_BRIDGE_IP:
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reg_rd_data <= bridge_ip_reg;
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REG_BRIDGE_UDP:
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reg_rd_data <= {16'b0, bridge_udp_port};
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REG_BRIDGE_ENABLE:
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reg_rd_data <= {31'b0,bridge_en};
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// Drop counts are used to debug situations
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// Where the incoming data goes faster than
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// chdr can consume it
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REG_CHDR_DROPPED:
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begin
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reg_rd_data <= chdr_drop_count;
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chdr_drop_count <= 0; // clear when read
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end
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REG_CPU_DROPPED:
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begin
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reg_rd_data <= cpu_drop_count;
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cpu_drop_count <= 0; // clear when read
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end
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REG_PAUSE:
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begin
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if (PAUSE_EN) begin
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reg_rd_data[15:0] <= my_pause_set;
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reg_rd_data[31:16] <= my_pause_clear;
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end
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end
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default:
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reg_rd_resp <= 1'b0;
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endcase
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end
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// Deassert read response after one clock cycle
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if (reg_rd_resp) begin
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reg_rd_resp <= 1'b0;
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end
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end
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end
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logic b_dropped_valid;
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logic e_cpu_dropped, b_cpu_dropped;
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logic e_chdr_dropped, b_chdr_dropped;
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// push over the clock domain
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// Sized to fit into 2 SRL's
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axi_fifo_2clk #(.WIDTH(2), .SIZE(4)) fifo_i (
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.reset(eth_rx.rst),
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.i_aclk(eth_rx.clk),
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.i_tdata({e_cpu_dropped, e_chdr_dropped}),
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.i_tvalid(e_cpu_dropped || e_chdr_dropped), .i_tready(/*not used*/),
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.o_aclk(bus_clk),
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.o_tdata({b_cpu_dropped, b_chdr_dropped}),
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.o_tvalid(b_dropped_valid), .o_tready(1'b1)
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);
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always_comb begin
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cpu_dropped = b_cpu_dropped && b_dropped_valid;
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chdr_dropped = b_chdr_dropped && b_dropped_valid;
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end
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eth_ipv4_chdr_adapter #(
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.PROTOVER (PROTOVER),
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.CPU_FIFO_SIZE (CPU_FIFO_SIZE),
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.CHDR_FIFO_SIZE (CHDR_FIFO_SIZE),
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.RT_TBL_SIZE (RT_TBL_SIZE),
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.NODE_INST (NODE_INST),
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.DROP_UNKNOWN_MAC(DROP_UNKNOWN_MAC),
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.DROP_MIN_PACKET (DROP_MIN_PACKET),
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.PREAMBLE_BYTES (PREAMBLE_BYTES),
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.ADD_SOF (ADD_SOF),
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.SYNC (SYNC),
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.ENET_W (ENET_W),
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.CPU_W (CPU_W),
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.CHDR_W (CHDR_W)
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) eth_adapter_i (
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.eth_pause_req (eth_pause_req),
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.eth_rx (eth_rx ),
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.eth_tx (eth_tx ),
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.v2e (v2e ),
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.e2v (e2v ),
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.c2e (c2e ),
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.e2c (e2c ),
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.device_id (device_id),
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.my_mac (my_mac ),
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.my_ip (my_ip ),
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.my_udp_chdr_port(my_udp_chdr_port),
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.my_pause_set (my_pause_set),
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.my_pause_clear (my_pause_clear),
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.chdr_dropped (e_chdr_dropped),
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.cpu_dropped (e_cpu_dropped)
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);
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endmodule : eth_ipv4_interface
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