319 lines
12 KiB
Verilog
319 lines
12 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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// radio top level module for b200
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// Contains all clock-rate DSP components, all radio and hardware controls and settings
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module radio_b200
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#(
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parameter FIFO_SIZE = 13
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)
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(input radio_clk, input radio_rst,
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input [31:0] rx, output [31:0] tx,
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inout [31:0] fe_atr, input pps,
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input bus_clk, input bus_rst,
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input [63:0] tx_tdata, input tx_tlast, input tx_tvalid, output tx_tready,
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output [63:0] rx_tdata, output rx_tlast, output rx_tvalid, input rx_tready,
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input [63:0] ctrl_tdata, input ctrl_tlast, input ctrl_tvalid, output ctrl_tready,
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output [63:0] resp_tdata, output resp_tlast, output resp_tvalid, input resp_tready,
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output [31:0] debug
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);
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// ///////////////////////////////////////////////////////////////////////////////
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// FIFO Interfacing to the bus clk domain
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// in_tdata splits to tx_tdata and ctrl_tdata
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// rx_tdata and resp_tdata get muxed to out_tdata
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// Everything except rx flow control must cross in to radio_clk domain before further use
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// _b signifies bus_clk domain, _r signifies radio_clk domain
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wire [63:0] ctrl_tdata_r;
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wire ctrl_tready_r, ctrl_tvalid_r;
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wire ctrl_tlast_r;
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wire [63:0] resp_tdata_r;
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wire resp_tready_r, resp_tvalid_r;
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wire resp_tlast_r;
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wire [63:0] rx_tdata_r;
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wire rx_tready_r, rx_tvalid_r;
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wire rx_tlast_r;
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wire [63:0] rx_mux_tdata_r;
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wire rx_mux_tready_r, rx_mux_tvalid_r;
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wire rx_mux_tlast_r;
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wire [63:0] rx_err_tdata_r;
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wire rx_err_tready_r, rx_err_tvalid_r;
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wire rx_err_tlast_r;
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wire [63:0] tx_tdata_r;
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wire tx_tready_r, tx_tvalid_r;
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wire tx_tlast_r;
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wire [63:0] txresp_tdata, txresp_tdata_r;
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wire txresp_tready, txresp_tready_r, txresp_tvalid, txresp_tvalid_r;
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wire txresp_tlast, txresp_tlast_r;
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wire [63:0] rmux_tdata_r;
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wire rmux_tlast_r, rmux_tvalid_r, rmux_tready_r;
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axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/)) ctrl_fifo
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(.reset(bus_rst),
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.i_aclk(bus_clk), .i_tvalid(ctrl_tvalid), .i_tready(ctrl_tready), .i_tdata({ctrl_tlast, ctrl_tdata}),
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.o_aclk(radio_clk), .o_tvalid(ctrl_tvalid_r), .o_tready(ctrl_tready_r), .o_tdata({ctrl_tlast_r, ctrl_tdata_r}));
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axi_fifo_2clk #(.WIDTH(65), .SIZE(FIFO_SIZE)) tx_fifo
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(.reset(bus_rst),
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.i_aclk(bus_clk), .i_tvalid(tx_tvalid), .i_tready(tx_tready), .i_tdata({tx_tlast, tx_tdata}),
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.o_aclk(radio_clk), .o_tvalid(tx_tvalid_r), .o_tready(tx_tready_r), .o_tdata({tx_tlast_r, tx_tdata_r}));
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axi_fifo_2clk #(.WIDTH(65), .SIZE(0/*minimal*/)) resp_fifo
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(.reset(radio_rst),
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.i_aclk(radio_clk), .i_tvalid(rmux_tvalid_r), .i_tready(rmux_tready_r), .i_tdata({rmux_tlast_r, rmux_tdata_r}),
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.o_aclk(bus_clk), .o_tvalid(resp_tvalid), .o_tready(resp_tready), .o_tdata({resp_tlast, resp_tdata}));
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axi_fifo_2clk #(.WIDTH(65), .SIZE(FIFO_SIZE)) rx_fifo
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(.reset(radio_rst),
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.i_aclk(radio_clk), .i_tvalid(rx_mux_tvalid_r), .i_tready(rx_mux_tready_r), .i_tdata({rx_mux_tlast_r, rx_mux_tdata_r}),
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.o_aclk(bus_clk), .o_tvalid(rx_tvalid), .o_tready(rx_tready), .o_tdata({rx_tlast, rx_tdata}));
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// /////////////////////////////////////////////////////////////////////////////////////
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// Setting bus and controls
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localparam SR_SPI = 8'd8;
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localparam SR_ATR = 8'd12;
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localparam SR_TEST = 8'd21;
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localparam SR_CODEC_IDLE = 8'd22;
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localparam SR_READBACK = 8'd32;
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localparam SR_TX_CTRL = 8'd64;
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localparam SR_RX_CTRL = 8'd96;
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localparam SR_RX_DSP = 8'd144;
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localparam SR_TX_DSP = 8'd184;
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localparam SR_TIME = 8'd128;
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localparam SR_RX_FMT = 8'd136;
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localparam SR_TX_FMT = 8'd138;
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wire set_stb;
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wire [7:0] set_addr;
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wire [31:0] set_data;
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wire [31:0] test_readback;
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wire run_rx, run_tx;
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reg [63:0] rb_data;
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wire [1:0] rb_addr;
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wire [63:0] vita_time, vita_time_lastpps;
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timekeeper #(.BASE(SR_TIME)) timekeeper
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(.clk(radio_clk), .reset(radio_rst), .pps(pps),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.vita_time(vita_time), .vita_time_lastpps(vita_time_lastpps));
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radio_ctrl_proc radio_ctrl_proc
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(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
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.ctrl_tdata(ctrl_tdata_r), .ctrl_tlast(ctrl_tlast_r), .ctrl_tvalid(ctrl_tvalid_r), .ctrl_tready(ctrl_tready_r),
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.resp_tdata(resp_tdata_r), .resp_tlast(resp_tlast_r), .resp_tvalid(resp_tvalid_r), .resp_tready(resp_tready_r),
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.vita_time(vita_time),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.ready(1'b1), .readback(rb_data),
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.debug());
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always @*
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case(rb_addr)
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2'd0 : rb_data <= { 32'b0, test_readback };
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2'd1 : rb_data <= vita_time;
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2'd2 : rb_data <= vita_time_lastpps;
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2'd3 : rb_data <= {tx, rx};
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default : rb_data <= 64'd0;
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endcase // case (rb_addr)
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setting_reg #(.my_addr(SR_TEST), .awidth(8), .width(32)) sr_test
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(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(test_readback), .changed());
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wire [31:0] tx_idle;
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setting_reg #(.my_addr(SR_CODEC_IDLE), .awidth(8), .width(32)) sr_codec_idle
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(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(tx_idle), .changed());
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setting_reg #(.my_addr(SR_READBACK), .awidth(8), .width(2)) sr_rdback
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(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(rb_addr), .changed());
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gpio_atr #(.BASE(SR_ATR), .WIDTH(32)) gpio_atr
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(.clk(radio_clk),.reset(radio_rst),
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.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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.rx(run_rx), .tx(run_tx),
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.gpio(fe_atr), .gpio_readback() );
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// /////////////////////////////////////////////////////////////////////////////////
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// TX Chain
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wire [175:0] txsample_tdata;
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wire txsample_tvalid, txsample_tready;
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wire [31:0] sample_tx;
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wire ack_or_error, packet_consumed;
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wire [11:0] seqnum;
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wire [63:0] error_code;
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wire [31:0] sid;
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wire [23:0] tx_fe_i, tx_fe_q;
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assign tx[31:16] = (run_tx)? tx_fe_i[23:8] : tx_idle[31:16];
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assign tx[15:0] = (run_tx)? tx_fe_q[23:8] : tx_idle[15:0];
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wire [63:0] tx_tdata_i; wire tx_tlast_i, tx_tvalid_i, tx_tready_i;
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new_tx_deframer tx_deframer
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(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
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.i_tdata(tx_tdata_i), .i_tlast(tx_tlast_i), .i_tvalid(tx_tvalid_i), .i_tready(tx_tready_i),
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.sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready));
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new_tx_control #(.BASE(SR_TX_CTRL)) tx_control
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(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.vita_time(vita_time),
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.ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
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.seqnum(seqnum), .error_code(error_code), .sid(sid),
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.sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready),
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.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
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.debug());
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tx_responder #(.BASE(SR_TX_CTRL+2)) tx_responder
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(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
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.seqnum(seqnum), .error_code(error_code), .sid(sid),
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.vita_time(vita_time),
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.o_tdata(txresp_tdata_r), .o_tlast(txresp_tlast_r), .o_tvalid(txresp_tvalid_r), .o_tready(txresp_tready_r));
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duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0), .WIDTH(24)) duc_chain
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(.clk(radio_clk), .rst(radio_rst), .clr(1'b0),
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.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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.tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
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.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
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.debug() );
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chdr_xxxx_to_16sc_chain #(.BASE(SR_TX_FMT)) convert_xxxx_to_16sc
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(.clk(radio_clk), .reset(radio_rst),
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.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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.i_tdata(tx_tdata_r), .i_tlast(tx_tlast_r), .i_tvalid(tx_tvalid_r), .i_tready(tx_tready_r),
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.o_tdata(tx_tdata_i), .o_tlast(tx_tlast_i), .o_tvalid(tx_tvalid_i), .o_tready(tx_tready_i));
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// /////////////////////////////////////////////////////////////////////////////////
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// RX Chain
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wire full, eob_rx;
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wire strobe_rx;
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wire [31:0] sample_rx;
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wire [31:0] rx_sid;
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wire [11:0] rx_seqnum;
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wire [63:0] rx_tdata_i; wire rx_tlast_i, rx_tvalid_i, rx_tready_i;
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new_rx_framer #(.BASE(SR_RX_CTRL+4)) new_rx_framer
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(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.vita_time(vita_time),
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.strobe(strobe_rx), .sample(sample_rx), .run(run_rx), .eob(eob_rx), .full(full),
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.sid(rx_sid), .seqnum(rx_seqnum),
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.o_tdata(rx_tdata_i), .o_tlast(rx_tlast_i), .o_tvalid(rx_tvalid_i), .o_tready(rx_tready_i),
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.debug());
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new_rx_control #(.BASE(SR_RX_CTRL)) new_rx_control
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(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.vita_time(vita_time),
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.strobe(strobe_rx), .run(run_rx), .eob(eob_rx), .full(full),
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.sid(rx_sid), .seqnum(rx_seqnum),
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.err_tdata(rx_err_tdata_r), .err_tlast(rx_err_tlast_r), .err_tvalid(rx_err_tvalid_r), .err_tready(rx_err_tready_r),
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.debug());
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ddc_chain #(.BASE(SR_RX_DSP), .DSPNO(0), .WIDTH(24)) ddc_chain
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(.clk(radio_clk), .rst(radio_rst), .clr(1'b0),
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.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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.rx_fe_i({rx[31:16],8'd0}),.rx_fe_q({rx[15:0],8'd0}),
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.sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
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.debug() );
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chdr_16sc_to_xxxx_chain #(.BASE(SR_RX_FMT)) convert_16sc_to_xxxx
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(.clk(radio_clk), .reset(radio_rst),
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.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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.i_tdata(rx_tdata_i), .i_tlast(rx_tlast_i), .i_tvalid(rx_tvalid_i), .i_tready(rx_tready_i),
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.o_tdata(rx_tdata_r), .o_tlast(rx_tlast_r), .o_tvalid(rx_tvalid_r), .o_tready(rx_tready_r));
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// /////////////////////////////////////////////////////////////////////////////////
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// RX Channel Muxing
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axi_mux4 #(.PRIO(1), .WIDTH(64)) rx_mux
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(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
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.i0_tdata(rx_tdata_r), .i0_tlast(rx_tlast_r), .i0_tvalid(rx_tvalid_r), .i0_tready(rx_tready_r),
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.i1_tdata(rx_err_tdata_r), .i1_tlast(rx_err_tlast_r), .i1_tvalid(rx_err_tvalid_r), .i1_tready(rx_err_tready_r),
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.i2_tdata(), .i2_tlast(), .i2_tvalid(1'b0), .i2_tready(),
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.i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(),
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.o_tdata(rx_mux_tdata_r), .o_tlast(rx_mux_tlast_r), .o_tvalid(rx_mux_tvalid_r), .o_tready(rx_mux_tready_r));
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// /////////////////////////////////////////////////////////////////////////////////
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// Response Channel Muxing
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axi_mux4 #(.PRIO(0), .WIDTH(64)) response_mux
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(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
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.i0_tdata(txresp_tdata_r), .i0_tlast(txresp_tlast_r), .i0_tvalid(txresp_tvalid_r), .i0_tready(txresp_tready_r),
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.i1_tdata(resp_tdata_r), .i1_tlast(resp_tlast_r), .i1_tvalid(resp_tvalid_r), .i1_tready(resp_tready_r),
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.i2_tdata(), .i2_tlast(), .i2_tvalid(1'b0), .i2_tready(),
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.i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(),
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.o_tdata(rmux_tdata_r), .o_tlast(rmux_tlast_r), .o_tvalid(rmux_tvalid_r), .o_tready(rmux_tready_r));
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wire [255:0] debug1;
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reg [255:0] debug2;
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/* -----\/----- EXCLUDED -----\/-----
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always @(posedge radio_clk)
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debug2 <= debug1;
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wire [35:0] CONTROL0,CONTROL1;
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chipscope_ila_256 chipscope_ila_256(
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.CONTROL(CONTROL0), // INOUT BUS [35:0]
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.CLK(radio_clk), // IN
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.TRIG0(debug2) // IN BUS [31:0]
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);
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chipscope_ila_32 chipscope_ila_32(
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.CONTROL(CONTROL1), // INOUT BUS [35:0]
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.CLK(radio_clk), // IN
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.TRIG0(32'd0) // IN BUS [31:0]
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);
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chipscope_icon chipscope_icon(
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.CONTROL0(CONTROL0), // INOUT BUS [35:0]
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.CONTROL1(CONTROL1) // INOUT BUS [35:0]
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);
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assign debug1 = {
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debug_tx_framer, // [214:206]
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debug_tx_control, // [205:177]
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set_data, // [176:145]
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set_addr, // [144:137]
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set_stb, // [136]
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run_tx, // [135]
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run_rx, // [134]
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tx_tlast, // [133]
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tx_tready, // [132]
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tx_tvalid, // [131]
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ctrl_tlast, // [130]
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ctrl_tready, // [129]
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ctrl_tvalid, // [128]
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tx_tdata, // [127:64]
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ctrl_tdata // [63:0]
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};
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-----/\----- EXCLUDED -----/\----- */
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endmodule // radio_b200
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