47 lines
1.2 KiB
Plaintext
47 lines
1.2 KiB
Plaintext
The following files were generated for 'chipscope_icon' in directory
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/home/ianb/fpgapriv_usrp3/fpgapriv/usrp3/top/b200/coregen/
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XCO file generator:
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Generate an XCO file for compatibility with legacy flows.
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* chipscope_icon.xco
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Creates an implementation netlist:
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Creates an implementation netlist for the IP.
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* chipscope_icon.constraints/chipscope_icon.ucf
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* chipscope_icon.constraints/chipscope_icon.xdc
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* chipscope_icon.ngc
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* chipscope_icon.ucf
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* chipscope_icon.v
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* chipscope_icon.veo
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* chipscope_icon.xdc
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* chipscope_icon_xmdf.tcl
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IP Symbol Generator:
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Generate an IP symbol based on the current project options'.
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* chipscope_icon.asy
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Generate ISE subproject:
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Create an ISE subproject for use when including this core in ISE designs
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* _xmsgs/pn_parser.xmsgs
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* chipscope_icon.gise
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* chipscope_icon.xise
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Deliver Readme:
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Readme file for the IP.
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* chipscope_icon_readme.txt
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Generate FLIST file:
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Text file listing all of the output files produced when a customized core was
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generated in the CORE Generator.
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* chipscope_icon_flist.txt
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Please see the Xilinx CORE Generator online help for further details on
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generated files and how to use them.
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