62 lines
854 B
Verilog
62 lines
854 B
Verilog
module iq_to_float_tb();
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reg clk, reset;
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integer x,file;
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reg [15:0] in;
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wire [31:0] out;
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initial clk = 0;
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always #10 clk = ~clk;
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initial $dumpfile("iq_to_float_tb.vcd");
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initial $dumpvars(0,iq_to_float_tb);
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integer f;
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initial
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begin
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x <= 0;
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reset <= 1;
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in <= 0;
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file = $fopen("iq_to_float_VER.txt");
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repeat(65536) @(posedge clk);
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reset <= 0;
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repeat(65536) @(posedge clk)
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begin
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in <= data[x];
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x <= x+1;
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$fdisplayh(file,out);
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end
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$fclose(file);
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repeat(65536) @(posedge clk);
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$finish;
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end
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iq_to_float #(.BITS_IN(16), .BITS_OUT(32))
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dut
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(
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.in(in), .out(out), .clk(clk), .reset(reset)
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);
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reg [15:0] data [0:65535];
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initial $readmemh("iq_to_float_input.txt",data);
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endmodule
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