93 lines
1.5 KiB
Verilog
93 lines
1.5 KiB
Verilog
module iq_to_float
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#(parameter BITS_IN =16,
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parameter BITS_OUT = 32
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)
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(
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input [15:0] in,
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output [31:0] out
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);
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//imaginary
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//2s complement
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wire [15:0] unsigned_mag;
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wire [15:0] complement;
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//leading bit registers
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wire [15:0] lead;
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wire [15:0] reversed_mag;
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//16-4 encoder
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wire [3:0] binary_out;
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wire [22:0] fraction;
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wire [7:0] exponent;
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wire [15:0] binary_in;
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binary_encoder #(.SIZE(16))
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encoding
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(.in(binary_in),.out(binary_out));
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// Detect sign, if negative detected perform 2's complement
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assign unsigned_mag = (in[15] == 1)?((~in[15:0])+1'b1):in[15:0];
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//detect leading one
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assign complement = ((~reversed_mag[BITS_IN-1:0])+1'b1);
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assign lead = complement & reversed_mag;
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//calculate fraction and exponent using shift value generated
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wire [15:0] pre_frac = unsigned_mag << ((15 - binary_out));
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assign fraction = {pre_frac[14:0],8'h0};
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assign exponent = (in == 16'b0)?(8'b0):(binary_out +'d127);
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//construct the output
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assign out = {in[15], exponent, fraction};
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//reverse the signed input
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genvar r;
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generate
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for (r = 0; r < 16; r = r+1) begin:bit_reverse
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assign reversed_mag[r] = unsigned_mag[BITS_IN-r-1];
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end
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endgenerate
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//reversed the output of the detect the leading bit procedure
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genvar i;
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generate
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for (i= 0; i < 16; i = i+1) begin: i_rev
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assign binary_in[i] = lead[BITS_IN-i-1];
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end
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endgenerate
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endmodule
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