222 lines
6.0 KiB
Verilog
222 lines
6.0 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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module chdr_16sc_to_12sc
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#(parameter BASE=0)
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( input set_stb, input [7:0] set_addr, input [31:0] set_data,
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//left side of device
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input clk, input reset,
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input [63:0] i_tdata,
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input i_tlast,
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input i_tvalid,
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output i_tready,
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//right side of device
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output reg [63:0] o_tdata = 0,
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output o_tlast,
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output o_tvalid,
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input o_tready,
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output [31:0] debug
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);
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wire chdr_has_hdr = 1'b1;
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wire chdr_has_time = i_tdata[61];
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wire chdr_has_tlr = 1'b0;
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wire [11:0] imag0;
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wire [11:0] real0;
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wire [11:0] imag1;
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wire [11:0] real1;
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wire [11:0] imag2;
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wire [11:0] real2;
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wire [16:0] round_i0;
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wire [16:0] round_r0;
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wire [16:0] round_i1;
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wire [16:0] round_r1;
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wire [16:0] round_i2;
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wire [16:0] round_r2;
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//pipiline registers
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reg [11:0] imag0_out;
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reg [11:0] real0_out;
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reg [11:0] imag1_out;
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reg [11:0] real1_out;
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reg [15:0] len_data;
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//chdr length calculations
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wire [15:0] chdr_header_lines = chdr_has_time? 16 : 8;
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wire [15:0] in_samples = i_tdata[47:32] - chdr_header_lines;
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wire [15:0] samples = (in_samples*3) >> 2;
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wire [15:0] chdr_payload_lines = samples + chdr_header_lines;
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reg needs_exline = 0;
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reg in_exline = 0;
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wire set_sid;
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wire [15:0] my_newhome;
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setting_reg #(.my_addr(BASE), .width(17)) new_destination
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(.clk(clk), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out({set_sid, my_newhome[15:0]}));
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//state machine
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localparam HEADER = 3'd0; // IDLE
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localparam TIME = 3'd1;
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localparam LINE_ODD_ZERO = 3'd2;
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localparam LINE_EVEN_ONE = 3'd3;
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localparam LINE_ODD_TWO = 3'd4;
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localparam REG_STATE = 3'd5;
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reg [2:0] state;
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always @(posedge clk) begin
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if (reset) begin
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state <= HEADER;
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needs_exline <= 0;
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in_exline <= 0;
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end
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else if ((o_tvalid && o_tready) || (i_tready && i_tvalid)) case(state)
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HEADER: begin
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needs_exline <= (in_samples[4:2] == 3 || in_samples[4:2] == 4 || in_samples[4:2] == 6);
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state <= (i_tdata[61])? TIME: REG_STATE;
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end
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TIME: begin
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state <= (i_tlast) ? HEADER: REG_STATE;
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end
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REG_STATE: begin
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if (i_tlast & !needs_exline || in_exline) begin
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state <= HEADER;
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in_exline <= 0;
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end
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else if (i_tlast & needs_exline) begin
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state <= LINE_EVEN_ONE;
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in_exline <= 1;
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end
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else
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state <= LINE_EVEN_ONE;
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end
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LINE_EVEN_ONE: begin
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if (i_tlast & !needs_exline || in_exline) begin
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state <= HEADER;
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in_exline <= 0;
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end
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else if (i_tlast & needs_exline) begin
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state <= LINE_ODD_TWO;
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in_exline <= 1;
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end
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else
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state <= LINE_ODD_TWO;
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end
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LINE_ODD_TWO: begin
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if (i_tlast & !needs_exline || in_exline) begin
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state <= HEADER;
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in_exline <= 0;
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end
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else if (i_tlast & needs_exline) begin
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state <= LINE_ODD_ZERO;
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in_exline <= 1;
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end
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else
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state <= LINE_ODD_ZERO;
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end
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LINE_ODD_ZERO: begin
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if (i_tlast & !needs_exline || in_exline) begin
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state <= HEADER;
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in_exline <= 0;
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end
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else if (i_tlast & needs_exline) begin
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state <= REG_STATE;
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in_exline <= 1;
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end
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else
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state <= REG_STATE;
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end
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default: state <= HEADER;
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endcase
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end
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assign round_i0 = ({i_tdata[63],i_tdata[63:48]} + 'h0008);
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assign round_r0 = ({i_tdata[47],i_tdata[47:32]} + 'h0008);
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assign imag0 = (round_i0[16] == 0 && round_i0[15] == 1)?(12'h7FF):(round_i0[16] == 1 && round_i0[15] == 0)? (12'h800):(round_i0[15:4]);
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assign real0 = (round_r0[16] == 0 && round_r0[15] == 1)?(12'h7FF):(round_r0[16] == 1 && round_r0[15] == 0)? (12'h800):(round_r0[15:4]);
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assign round_i1 = ({i_tdata[31],i_tdata[31:16]} + 'h0008);
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assign round_r1 = ({i_tdata[15],i_tdata[15:0]} + 'h0008);
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assign imag1 = (round_i1[16] == 0 && round_i1[15] == 1)?(12'h7FF):(round_i1[16] == 1 && round_i1[15] == 0)? (12'h800):(round_i1[15:4]);
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assign real1 = (round_r1[16] == 0 && round_r1[15] == 1)?(12'h7FF):(round_r1[16] == 1 && round_r1[15] == 0)? (12'h800):(round_r1[15:4]);
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always @(posedge clk)
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if (i_tvalid && o_tready)
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begin
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imag0_out <= imag0;
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real0_out <= real0;
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imag1_out <= imag1;
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real1_out <= real1;
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end
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always @(*)
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case(state)
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HEADER: o_tdata <= {i_tdata[63:48], chdr_payload_lines,
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set_sid ? {i_tdata[15:0], my_newhome[15:0]}:i_tdata[31:0]};
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TIME: o_tdata <= i_tdata;
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REG_STATE: o_tdata <= {imag0,real0,imag1, real1, 16'b0};
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LINE_EVEN_ONE: o_tdata <= {imag0_out, real0_out, imag1_out, real1_out, imag0, real0[11:8]};
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LINE_ODD_TWO: o_tdata <= {real0_out[7:0], imag1_out, real1_out, imag0, real0,imag1[11:4]};
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LINE_ODD_ZERO: o_tdata <= {imag1_out[3:0], real1_out, imag0, real0, imag1, real1};
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default : o_tdata <= i_tdata;
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endcase
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assign o_tvalid =((in_exline) || (state != REG_STATE & i_tvalid) || (i_tlast & i_tvalid & !needs_exline));
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assign i_tready = (o_tready & !in_exline)||(state == REG_STATE && !i_tlast);
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assign o_tlast = (needs_exline)? in_exline: i_tlast;
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endmodule
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