52 lines
1.1 KiB
Verilog
52 lines
1.1 KiB
Verilog
//
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// Copyright 2011-2012 Ettus Research LLC
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//
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// 64 bits worth of ticks
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//
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// Not concerned with clock wrapping, human race will likely have extermintated it's self by this time.
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//
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module time_compare
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(
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input clk,
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input reset,
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input [63:0] time_now,
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input [63:0] trigger_time,
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output now,
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output early,
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output late,
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output too_early);
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/*
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reg [63:0] time_diff;
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always @(posedge clk) begin
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if (reset) begin
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time_diff <= 64'b0;
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now <= 1'b0;
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late <= 1'b0;
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early <= 1'b0;
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end
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else begin
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time_diff <= trigger_time - time_now;
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now <= ~(|time_diff);
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late <= time_diff[63];
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early <= ~now & ~late;
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end
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end
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//assign now = ~(|time_diff);
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//assign late = time_diff[63];
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//assign early = ~now & ~late;
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assign too_early = 0; //not implemented
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*/
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assign now = time_now == trigger_time;
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assign late = time_now > trigger_time;
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assign early = ~now & ~late;
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assign too_early = 0; //not implemented
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endmodule // time_compare
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