312 lines
6.8 KiB
Verilog
312 lines
6.8 KiB
Verilog
//
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// Copyright 2012 Ettus Research LLC
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//
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`timescale 1 ps / 1 ps
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module eth_dispatch_tb();
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// Clocking and reset interface
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reg clk;
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reg reset;
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reg clear;
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// Setting register interface
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reg set_stb;
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reg [15:0] set_addr;
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reg [31:0] set_data;
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// Input 68bit AXI-Stream interface (from MAC)
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wire [63:0] in_tdata;
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wire [3:0] in_tuser;
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wire in_tlast;
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wire in_tvalid;
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wire in_tready;
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// Output AXI-Stream interface to VITA Radio Core
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wire [63:0] vita_tdata;
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wire [3:0] vita_tuser;
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wire vita_tlast;
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wire vita_tvalid;
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wire vita_tready;
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// Output AXI-Stream interface to ZPU
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wire [63:0] zpu_tdata;
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wire [3:0] zpu_tuser;
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wire zpu_tlast;
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wire zpu_tvalid;
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wire zpu_tready;
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// Output AXI-Stream interface to cross-over MAC
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wire [63:0] xo_tdata;
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wire [3:0] xo_tuser;
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wire xo_tlast;
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wire xo_tvalid;
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wire xo_tready;
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reg [63:0] data_in;
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reg [3:0] user_in;
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reg valid_in;
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wire ready_in;
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reg last_in;
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eth_dispatch
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#(.BASE(0))
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eth_dispatch_i
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(
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// Clocking and reset interface
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.clk(clk),
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.reset(reset),
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.clear(clear),
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// Setting register interface
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.set_stb(set_stb),
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.set_addr(set_addr),
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.set_data(set_data),
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// Input 68bit AXI-Stream interface (from MAC)
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.in_tdata(in_tdata),
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.in_tuser(in_tuser),
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.in_tlast(in_tlast),
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.in_tvalid(in_tvalid),
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.in_tready(in_tready),
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// Output AXI-STream interface to VITA Radio Core
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.vita_tdata(vita_tdata),
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.vita_tuser(vita_tuser),
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.vita_tlast(vita_tlast),
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.vita_tvalid(vita_tvalid),
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.vita_tready(vita_tready),
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// Output AXI-Stream interface to ZPU
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.zpu_tdata(zpu_tdata),
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.zpu_tuser(zpu_tuser),
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.zpu_tlast(zpu_tlast),
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.zpu_tvalid(zpu_tvalid),
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.zpu_tready(zpu_tready),
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// Output AXI-Stream interface to cross-over MAC
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.xo_tdata(xo_tdata),
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.xo_tuser(xo_tuser),
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.xo_tlast(xo_tlast),
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.xo_tvalid(xo_tvalid),
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.xo_tready(xo_tready)
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);
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//
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// Define Clocks
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//
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initial begin
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clk = 1'b1;
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end
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// 125MHz clock
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always #4000 clk = ~clk;
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//
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// Good starting state
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//
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initial begin
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reset <= 0;
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clear <= 0;
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set_stb <= 0;
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set_addr <= 0;
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set_data <= 0;
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data_in <= 0;
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user_in <= 0;
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valid_in <= 0;
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last_in <= 0;
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end
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//
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// Task Libaray
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//
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task write_setting_bus;
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input [15:0] address;
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input [31:0] data;
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begin
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@(negedge clk);
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set_stb = 1'b0;
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set_addr = 16'h0;
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set_data = 32'h0;
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@(negedge clk);
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set_stb = 1'b1;
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set_addr = address;
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set_data = data;
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@(negedge clk);
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set_stb = 1'b0;
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set_addr = 16'h0;
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set_data = 32'h0;
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end
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endtask // write_setting_bus
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task enqueue_line;
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input last;
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input [2:0] keep;
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input [63:0] data;
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begin
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data_in <= {keep, data};
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last_in <= last;
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valid_in <= 1;
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while (~ready_in) begin
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@(negedge clk);
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end
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@(negedge clk);
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data_in <= 0;
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last_in <= 0;
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valid_in <= 0;
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end
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endtask // enqueue_line
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task enqueue_arp_req;
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input [47:0] src_mac;
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input [31:0] src_ip;
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input [47:0] dst_mac;
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input [31:0] dst_ip;
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begin
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@(negedge clk);
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// Line 0
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enqueue_line( 0, 3'b0, {48'h0,16'hffff});
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// Line 1 - Eth
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enqueue_line( 0, 3'b0, {32'hffffffff,src_mac[47:16]});
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// Line 2 - Eth+ARP (HTYPE = 1, PTYPE = 0x0800)
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enqueue_line( 0, 3'b0, {src_mac[15:0],16'h0806,16'h0001,16'h0800});
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// Line 3 - HLEN=6, PLEN=4 OPER=1
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enqueue_line( 0, 3'b0, {8'h06,8'h04,16'h0001,src_mac[47:16]});
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// Line 4 - ARP
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enqueue_line( 0, 3'b0, {src_mac[15:0],src_ip[31:0],dst_mac[47:32]});
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// Line 5 - ARP
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enqueue_line( 1, 3'b0, {dst_mac[31:0],dst_ip[31:0]});
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end
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endtask // enqueue_arp_req
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reg [11:0] frame_count =12'h0;
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task enqueue_vita_pkt;
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// We assume that we always have SID and TSF fields.
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input [47:0] mac;
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input [31:0] ip;
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input [15:0] udp;
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input [15:0] vita_size;
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input [63:0] vita_tsf;
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input [31:0] vita_sid;
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integer i;
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reg [15:0] j;
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reg [19:0] vrl_size;
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reg [15:0] udp_size;
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reg [15:0] ip_size;
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begin
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vrl_size = vita_size + 3;
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udp_size = vrl_size*4 + 8;
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ip_size = udp_size + 20;
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@(negedge clk);
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// Line 0
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enqueue_line( 0, 3'b0, {48'h0,mac[47:32]});
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// Line 1 - Eth
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enqueue_line( 0, 3'b0, {mac[31:0],32'h11223344});
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// Line 2 - Eth+IP
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enqueue_line( 0, 3'b0, {16'h5566,16'h0800,16'h0000,ip_size});
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// Line 3 - IP
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enqueue_line( 0, 3'b0, 'h11<<16);
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// Line 4 - IP
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enqueue_line( 0, 3'b0, {32'h09080706, ip});
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// Line 5 - UDP
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enqueue_line( 0, 3'b0, {16'h1234, udp, udp_size, 16'h0});
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// Line 6 - VRL
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enqueue_line( 0, 3'b0, {"VRLP",frame_count,vrl_size});
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// Line 7 - VRT
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enqueue_line( 0, 3'b0, {16'b0001000000010000, vita_size,vita_sid}); //vita hdr + SID
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enqueue_line( 0, 3'b0, vita_tsf);
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j = 0;
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for (i = 6; i < vita_size; i = i + 2) begin
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enqueue_line( 0 , 3'b0, {j,j+16'h1,j+16'h2,j+16'h3});
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j = j + 4;
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end
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if (i-vita_size==0) // 2x32words to finish VITA packet.
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enqueue_line( 1, 3'b0, {j,j+16'h1,j+16'h2,j+16'h3});
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else // 1x32bit word to finish VITA packet
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enqueue_line( 1, 3'h4, {j,j+16'h1,j+16'h2,j+16'h3});
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end
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endtask // enqueue_packet
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//
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// Simulation specific testbench is included here
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//
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`include "simulation_script.v"
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//
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// Input FIFO
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//
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axi_fifo_short
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#(.WIDTH(69)) axi_fifo_short_in
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(
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.clk(clk),
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.reset(reset),
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.clear(clear),
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.o_tdata({in_tlast,in_tuser,in_tdata}),
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.o_tvalid(in_tvalid),
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.o_tready(in_tready),
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.i_tdata({last_in,user_in,data_in}),
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.i_tvalid(valid_in),
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.i_tready(ready_in),
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.space(),
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.occupied()
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);
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//
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// Output Sinks
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//
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axi_probe_tb
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#(.FILENAME("zpu.txt"),.VITA_PORT0(60000),.VITA_PORT1(60001)) axi_probe_tb_zpu
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(
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.clk(clk),
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.reset(reset),
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.clear(clear),
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.tdata(zpu_tdata),
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.tvalid(zpu_tvalid),
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.tready(zpu_tready),
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.tlast(zpu_tlast)
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);
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assign zpu_tready = 1'b1;
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axi_probe_tb
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#(.FILENAME("xo.txt"),.VITA_PORT0(60000),.VITA_PORT1(60001)) axi_probe_tb_xo
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(
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.clk(clk),
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.reset(reset),
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.clear(clear),
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.tdata(xo_tdata),
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.tvalid(xo_tvalid),
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.tready(xo_tready),
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.tlast(xo_tlast)
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);
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assign xo_tready = 1'b1;
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axi_probe_tb
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#(.FILENAME("vita.txt"),.VITA_PORT0(60000),.VITA_PORT1(60001),.START_AT_VRL(1)) axi_probe_tb_vita
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(
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.clk(clk),
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.reset(reset),
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.clear(clear),
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.tdata(vita_tdata),
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.tvalid(vita_tvalid),
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.tready(vita_tready),
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.tlast(vita_tlast)
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);
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assign vita_tready = 1'b1;
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endmodule // eth_dispatch_tb
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