79 lines
2.8 KiB
Verilog
79 lines
2.8 KiB
Verilog
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module compressed_vita_to_vrlp
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(input clk, input reset, input clear,
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input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
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output [63:0] o_tdata, output [15:0] o_tuser, output o_tlast, output o_tvalid, input o_tready
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);
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wire [19:0] vrlp_size = 20'd3 + {4'b0000,i_tdata[47:32]};
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reg odd_len;
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reg [2:0] cv2v_state;
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reg [63:0] o_tdata_int;
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wire o_tlast_int, o_tvalid_int, o_tready_int;
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localparam CV2V_VRLP = 3'd0; // VRLP header
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localparam CV2V_VRT_ECH = 3'd1; // Extension context header
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localparam CV2V_VRT_IFH = 3'd2; // IF Data header
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localparam CV2V_BODY = 3'd3;
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localparam CV2V_VEND_ODD = 3'd4;
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localparam CV2V_VEND_EVEN = 3'd4;
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always @(posedge clk)
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if(reset | clear)
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begin
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cv2v_state <= CV2V_VRLP;
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odd_len <= 1'b0;
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end
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else
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case(cv2v_state)
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CV2V_VRLP :
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if(i_tvalid & o_tready_int)
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begin
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odd_len <= i_tdata[32];
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if(i_tdata[63])
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cv2v_state <= CV2V_VRT_ECH;
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else
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cv2v_state <= CV2V_VRT_IFH;
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end
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CV2V_VRT_ECH, CV2V_VRT_IFH :
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if(i_tvalid & o_tready_int)
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cv2v_state <= CV2V_BODY;
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CV2V_BODY :
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if(i_tlast & i_tvalid & o_tready_int)
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if(odd_len)
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cv2v_state <= CV2V_VRLP;
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else
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cv2v_state <= CV2V_VEND_EVEN;
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CV2V_VEND_EVEN :
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if(o_tready_int)
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cv2v_state <= CV2V_VRLP;
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endcase // case (cv2v_state)
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assign i_tready = o_tready_int & (cv2v_state != CV2V_VRLP) & (cv2v_state != CV2V_VEND_EVEN);
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assign o_tvalid_int = i_tvalid | (cv2v_state == CV2V_VEND_EVEN);
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always @*
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case(cv2v_state)
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CV2V_VRLP : o_tdata_int <= { 32'h5652_4c50 /*VRLP*/, i_tdata[59:48] /*seqnum*/, vrlp_size[19:0] };
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CV2V_VRT_ECH : o_tdata_int <= { 4'h5 /*type*/, 4'h0, 3'b00, i_tdata[61] /*time*/, i_tdata[51:48] /*seqnum*/, i_tdata[47:32] /*len*/, i_tdata[31:0] /*sid*/ };
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CV2V_VRT_IFH : o_tdata_int <= { 4'h1 /*type*/, 1'b0, i_tdata[62] /*TRL*/, 1'b0, i_tdata[60] /*eob*/, 3'b00, i_tdata[61] /*time*/, i_tdata[51:48] /*seqnum*/, i_tdata[47:32] /*len*/, i_tdata[31:0] /*sid*/ };
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CV2V_BODY : o_tdata_int <= (i_tlast & odd_len) ? { i_tdata[63:32], 32'h5645_4E44 /*VEND*/ } : i_tdata;
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CV2V_VEND_EVEN : o_tdata_int <= { 32'h5645_4E44 /*VEND*/, 32'h0};
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default : o_tdata_int <= i_tdata;
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endcase // case (cv2v_state)
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assign o_tlast_int = (cv2v_state == CV2V_VEND_EVEN) | ((cv2v_state == CV2V_BODY) & i_tlast & odd_len);
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// Short FIFO before output
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axi_fifo_short #(.WIDTH(81)) axi_fifo_short
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata({o_tlast_int, i_tdata[15:0], o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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.o_tdata({o_tlast, o_tuser, o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
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.space(), .occupied());
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endmodule // compressed_vita_to_vrlp
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