165 lines
5.4 KiB
Verilog
165 lines
5.4 KiB
Verilog
//
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// Copyright 2011-2013 Ettus Research LLC
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//
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//! The USRP digital down-conversion chain
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module ddc_chain
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#(
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parameter BASE = 0,
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parameter DSPNO = 0,
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parameter WIDTH = 24
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)
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(input clk, input rst, input clr,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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// From RX frontend
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input [WIDTH-1:0] rx_fe_i,
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input [WIDTH-1:0] rx_fe_q,
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// To RX control
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output [31:0] sample,
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input run,
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output strobe,
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output [31:0] debug
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);
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localparam cwidth = 25;
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localparam zwidth = 24;
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wire [31:0] phase_inc;
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reg [31:0] phase;
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wire [17:0] scale_factor;
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wire [cwidth-1:0] i_cordic, q_cordic;
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wire [WIDTH-1:0] i_cordic_clip, q_cordic_clip;
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wire [WIDTH-1:0] i_cic, q_cic;
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wire [WIDTH-1:0] i_hb1, q_hb1;
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wire [WIDTH-1:0] i_hb2, q_hb2;
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wire strobe_cic, strobe_hb1, strobe_hb2;
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wire enable_hb1, enable_hb2;
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wire [7:0] cic_decim_rate;
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reg [WIDTH-1:0] rx_fe_i_mux, rx_fe_q_mux;
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wire realmode;
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wire swap_iq;
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setting_reg #(.my_addr(BASE+0)) sr_0
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(phase_inc),.changed());
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setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(scale_factor),.changed());
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setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
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setting_reg #(.my_addr(BASE+3), .width(2)) sr_3
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({realmode,swap_iq}),.changed());
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// MUX so we can do realmode signals on either input
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always @(posedge clk)
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if(swap_iq)
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begin
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rx_fe_i_mux <= rx_fe_q;
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rx_fe_q_mux <= realmode ? 0 : rx_fe_i;
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end
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else
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begin
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rx_fe_i_mux <= rx_fe_i;
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rx_fe_q_mux <= realmode ? 0 : rx_fe_q;
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end
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// NCO
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always @(posedge clk)
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if(rst)
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phase <= 0;
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else if(~run)
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phase <= 0;
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else
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phase <= phase + phase_inc;
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//sign extension of cordic input
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wire [cwidth-1:0] to_cordic_i, to_cordic_q;
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sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_i (.in(rx_fe_i_mux), .out(to_cordic_i));
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sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_q (.in(rx_fe_q_mux), .out(to_cordic_q));
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// CORDIC 24-bit I/O
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cordic_z24 #(.bitwidth(cwidth))
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cordic(.clock(clk), .reset(rst), .enable(run),
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.xi(to_cordic_i),. yi(to_cordic_q), .zi(phase[31:32-zwidth]),
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.xo(i_cordic),.yo(q_cordic),.zo() );
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clip_reg #(.bits_in(cwidth), .bits_out(WIDTH)) clip_i
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(.clk(clk), .in(i_cordic), .strobe_in(1'b1), .out(i_cordic_clip));
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clip_reg #(.bits_in(cwidth), .bits_out(WIDTH)) clip_q
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(.clk(clk), .in(q_cordic), .strobe_in(1'b1), .out(q_cordic_clip));
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// CIC decimator 24 bit I/O
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cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
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.strobe_fast(1),.strobe_slow(strobe_cic) );
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cic_decim #(.bw(WIDTH))
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decim_i (.clock(clk),.reset(rst),.enable(run),
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.rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
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.signal_in(i_cordic_clip),.signal_out(i_cic));
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cic_decim #(.bw(WIDTH))
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decim_q (.clock(clk),.reset(rst),.enable(run),
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.rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
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.signal_in(q_cordic_clip),.signal_out(q_cic));
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// First (small) halfband 24 bit I/O
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small_hb_dec #(.WIDTH(WIDTH)) small_hb_i
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(.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
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.stb_in(strobe_cic),.data_in(i_cic),.stb_out(strobe_hb1),.data_out(i_hb1));
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small_hb_dec #(.WIDTH(WIDTH)) small_hb_q
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(.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
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.stb_in(strobe_cic),.data_in(q_cic),.stb_out(),.data_out(q_hb1));
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// Second (large) halfband 24 bit I/O
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wire [8:0] cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate};
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hb_dec #(.WIDTH(WIDTH)) hb_i
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(.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
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.stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2));
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hb_dec #(.WIDTH(WIDTH)) hb_q
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(.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
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.stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
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//scalar operation (gain of 6 bits)
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wire [35:0] prod_i, prod_q;
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MULT18X18S mult_i
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(.P(prod_i), .A(i_hb2[WIDTH-1:WIDTH-18]), .B(scale_factor), .C(clk), .CE(strobe_hb2), .R(rst) );
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MULT18X18S mult_q
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(.P(prod_q), .A(q_hb2[WIDTH-1:WIDTH-18]), .B(scale_factor), .C(clk), .CE(strobe_hb2), .R(rst) );
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//pipeline for the multiplier (gain of 10 bits)
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reg [WIDTH-1:0] prod_reg_i, prod_reg_q;
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reg strobe_mult;
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always @(posedge clk) begin
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strobe_mult <= strobe_hb2;
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prod_reg_i <= prod_i[33:34-WIDTH];
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prod_reg_q <= prod_q[33:34-WIDTH];
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end
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// Round final answer to 16 bits
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round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(16)) round_i
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(.clk(clk),.reset(rst), .in(prod_reg_i),.strobe_in(strobe_mult), .out(sample[31:16]), .strobe_out(strobe));
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round_sd #(.WIDTH_IN(WIDTH),.WIDTH_OUT(16)) round_q
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(.clk(clk),.reset(rst), .in(prod_reg_q),.strobe_in(strobe_mult), .out(sample[15:0]), .strobe_out());
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assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_hb1, strobe_hb2};
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endmodule // ddc_chain
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