61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
131 lines
5.4 KiB
Tcl
131 lines
5.4 KiB
Tcl
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# Shared constants for the X410 FPGA and the ZBX CPLD.
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#
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# These output delays are more or less arbitrarily chosen, but they dictate the
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# delays at the input of the DB CPLD.
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# Since the CPLD is built in Quartus, the file extension is .sdc.
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set synth_sync_hold_requirement 1.0
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set synth_sync_setup_requirement 8.5
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# A MC100EPT23 clock translator is placed on the daughterboard to convert
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# pll_ref_clk clock IO Standard to 3.3V. The minimum and maximum delays across
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# this part are 1.1 ns and 1.8 ns, respectively.
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# https://www.onsemi.com/pub/Collateral/MC100EPT23-D.PDF
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set clock_translate_min 1.1
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set clock_translate_max 1.8
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## DB GPIO interface.
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# The following values have been adjusted after verifying the slack on input
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# and output path for the Post-synthesized designs for FPGA (Vivado) and CPLD
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# (Quartus). Values are chosen as those that provide the most slack for FPGA
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# timing, while still meeting timing on the CPLD.
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# FPGA output constraints
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set db_gpio_fpga_min_out 0.000
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set db_gpio_fpga_max_out 3.250
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# CPLD output constraints
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set db_gpio_cpld_min_out -2.000
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set db_gpio_cpld_max_out 8.500
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# The longest traces on the DB GPIO interface.
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# In order to compute the db_gpio_board_max_delay, the longest GPIO trace from
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# the FPGA to any of the DB connector was simulated, and its worst-case value
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# was added to the worst-case value obtained while simulating the longest GPIO
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# trace on the DB. Both directions (FPGA <-> CPLD) were considered when
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# computing the longest propagation delays. Propagation through the Board to
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# board connector is assumed shorter than the effect of having the edge
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# propagation time twice, as well as adding the two longest traces, instead of
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# the longest corresponding pair.
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# Longest trace | Trace length | Worst-case delay
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# MB: DB0_GPIO[19] | 4.25 in | 912 ps
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# DB: MB_FPGA_GPIO_A8 | 3.83 in | 862 ps
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set db_gpio_board_max_delay 1.774
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# The shortest traces on the DB GPIO interface are (assuming 170.0 ps/in).
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# A similar consideration was made as for db_gpio_board_max_delay, but using
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# the shortest traces in each CCA.
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# In this case, edge propagation was not taken into account, as the trace delay
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# can act as the worst-case minimum.
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# Shorted trace | Trace length | Trace delay
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# MB: DB1_GPIO[8] | 2.23 in | 379 ps
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# DB: MB_FPGA_GPIO_B12| 2.57 in | 436 ps
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set db_gpio_board_min_delay 0.815
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# DB and FPGA both use PLL reference clock from a common clock chip.
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# The common chip that drives these clocks is a LMK04832.
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# There exist two additional clock buffers within the trace taking the clock to
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# the daughterboard CPLD, a ADCLK944 located in the DB, and a MC100EPT23 near
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# the CPLD which takes care of level translation.
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# The largest delay that can exist between clocks exists when the LMK04832
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# presents its max skew between outputs and when all clock buffers present
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# their maximum delay.
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# MC100EPT23 propagation delays will be handled separately in constraints due
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# to their significant impact in timing closure, as well as to enable support
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# for various corner-cases.
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# Board delays were simulated in HyperLynx. Minimum delays considered time
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# between start of edge at the source to the start of edge at destination.
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# Maximum delays considered time between the start of an edge at the source and
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# the settling of the edge at destination. Corner cases were considered for IC
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# modeling.
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#
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# The clock path to the FPGA is composed by a single trace:
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# - Minimum clock propagation delay to FPGA = 815 ps.
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# - Maximum clock propagation delay to FPGA = 1.329 ps.
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#
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# The clock path to the CPLD (w/o MC100EPT23) is comprised by multiple traces:
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# - Path from MB LMK04832 to DB connector
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# - Minimum delay : 1636 ps
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# - Path from DB Connector to DB ADCLK944
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# - Minimum delay : 299 ps
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# - Path from DB ADCLK944 to CPLD:
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# - Minimum delay : 197 ps
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#
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# The clock path to the CPLD (w/ MC100EPT23) is comprised of multiple traces:
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# - Path from MB LMK04832 to DB connector
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# - Minimum delay : 1636 ps
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# - Maximum delay : 1890 ps
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# - Path from DB Connector to DB ADCLK944
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# - Minimum delay : 299 ps
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# - Maximum delay : 397 ps
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# - Path from DB ADCLK944 to MC100EPT23:
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# - Minimum delay : 120 ps
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# - Maximum delay : 411 ps
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# - Path from MC100EPT23 to CPLD:
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# - Minimum delay : 365 ps
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# - Maximum delay : 847 ps
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#
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# The minimum and maximum delays for all traces can be added to account for the
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# total board delay to the CPLD:
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#
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# Max total Board delay = 1890 + 397 + 411 + 847 = 3545 ps
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#
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# Min total Board delay = 1636 + 299 + 197 = 2132 ps
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# This leaves the worst-case clock arrival values for the different ICs as:
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# Max total Board delay + (Max LMK Skew) + (Max DB ADCLK Prop)
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# 3.545 + .1 + .130 = 3.775 ns,
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set db_cpld_prc_clock_prop_max 3.775
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# Min total Board delay - (Max LMK Skew) + (Min DB ADCLK Prop)
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# 2.132 - .1 + .07 = 2.102 ns,
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set db_cpld_prc_clock_prop_min 2.102
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# Board delay + (Max LMK Skew)
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# 1.329 + .1 = 1.429 ns
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set fpga_prc_clock_prop_max 1.429
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# Board delay - (Max LMK Skew)
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# .815 - .1 = 0.715 ns
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set fpga_prc_clock_prop_min 0.715
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# When combining these values, the LMK Skew will be accounted for twice,
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# which will just result in more conservative constraints.
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