117 lines
4.2 KiB
Verilog
117 lines
4.2 KiB
Verilog
//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axis_combine
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//
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// Description:
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//
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// Combines AXI stream buses into one output bus with concatenated data signals.
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//
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// Parameters:
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//
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// SIZE : The number of inputs streams to combine.
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// WIDTH : The width of TDATA on the input streams, if they are all the
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// same width. If they are different widths, then use WIDTH_VEC
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// instead.
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// WIDTH_VEC : A vector of widths corresponding to each stream's TDATA width.
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// Each number in this vector must be 32 bits wide. This defaults
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// to WIDTH bits for all inputs.
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// USER_WIDTH : The width of TUSER on the input streams, if they are all the
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// same width. If they are different widths, then use USER_WIDTH_VEC
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// instead.
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// USER_WIDTH_VEC : A vector of widths corresponding to each stream's TUSER width.
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// Each number in this vector must be 32 bits wide. This defaults
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// to USER_WIDTH bits for all inputs.
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// FIFO_SIZE_LOG2 : Log2 the size of the FIFO to use internally for each stream.
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//
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`default_nettype none
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module axis_combine #(
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parameter SIZE = 2,
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parameter WIDTH = 32,
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parameter USER_WIDTH = 1,
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parameter [32*SIZE-1:0] WIDTH_VEC = {SIZE{WIDTH[31:0]}},
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parameter [32*SIZE-1:0] USER_WIDTH_VEC = {SIZE{USER_WIDTH[31:0]}},
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parameter FIFO_SIZE_LOG2 = 0
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) (
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input wire clk,
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input wire reset,
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// Input streams
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input wire [len(SIZE-1, WIDTH_VEC)-1:0] s_axis_tdata,
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input wire [len(SIZE-1,USER_WIDTH_VEC)-1:0] s_axis_tuser,
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input wire [ SIZE-1:0] s_axis_tlast,
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input wire [ SIZE-1:0] s_axis_tvalid,
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output wire [ SIZE-1:0] s_axis_tready,
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// Output streams
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output wire [len(SIZE-1, WIDTH_VEC)-1:0] m_axis_tdata,
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output wire [len(SIZE-1,USER_WIDTH_VEC)-1:0] m_axis_tuser,
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output wire m_axis_tlast,
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output wire m_axis_tvalid,
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input wire m_axis_tready
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);
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// Helper function to calculate the combined length of the lower 'n' ports
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// based on the concatenated widths (each 32-bits wide) stored in width_vector.
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// Note: If n is negative, returns 0.
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function automatic integer len(input integer n, input [32*SIZE-1:0] width_vector);
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integer i, total;
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begin
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total = 0;
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if (n >= 0) begin
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for (i = 0; i <= n; i = i + 1) begin
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total = total + width_vector[32*i +: 32];
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end
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end
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len = total;
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end
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endfunction
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wire [len(SIZE-1, WIDTH_VEC)-1:0] int_tdata;
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wire [len(SIZE-1,USER_WIDTH_VEC)-1:0] int_tuser;
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wire [ SIZE-1:0] int_tlast;
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wire [ SIZE-1:0] int_tvalid;
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wire [ SIZE-1:0] int_tready;
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// Generate a FIFO for each stream
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genvar i;
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generate
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for (i = 0; i < SIZE; i = i + 1) begin
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axi_fifo #(
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.WIDTH (WIDTH_VEC[32*i +: 32] + USER_WIDTH_VEC[32*i +: 32] + 1),
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.SIZE (FIFO_SIZE_LOG2)
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) axi_fifo (
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.clk (clk),
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.reset (reset),
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.clear (),
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.i_tdata ({ s_axis_tlast[i],
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s_axis_tuser[len(i,USER_WIDTH_VEC)-1 : len(i-1,USER_WIDTH_VEC)],
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s_axis_tdata[len(i, WIDTH_VEC)-1 : len(i-1, WIDTH_VEC)] }),
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.i_tvalid (s_axis_tvalid[i]),
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.i_tready (s_axis_tready[i]),
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.o_tdata ({ int_tlast[i],
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int_tuser[len(i,USER_WIDTH_VEC)-1 : len(i-1,USER_WIDTH_VEC)],
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int_tdata[len(i, WIDTH_VEC)-1 : len(i-1, WIDTH_VEC)] }),
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.o_tvalid (int_tvalid[i]),
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.o_tready (int_tready[i]),
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.space (),
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.occupied ()
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);
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end
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endgenerate
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assign int_tready = { SIZE {m_axis_tvalid & m_axis_tready} };
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assign m_axis_tvalid = &int_tvalid;
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assign m_axis_tdata = int_tdata;
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assign m_axis_tuser = int_tuser;
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assign m_axis_tlast = int_tlast;
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endmodule
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`default_nettype wire
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