61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
52 lines
1.3 KiB
VHDL
52 lines
1.3 KiB
VHDL
--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: scale_2x
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--
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-- Description:
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--
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-- This block does the scaling of IQ data by 2. The data from the mixer is
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-- 1/2 the full scale and the upper two bits will only have the signed bits,
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-- so it is okay to multiply the data by 2 and resize it back to 16 bits.
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--
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-- Parameters:
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--
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-- kDataWidth: Data width, should be a multiple of 16 bits.
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library WORK;
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use WORK.PkgRf.all;
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entity scale_2x is
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generic(
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kDataWidth : integer range 1 to 256 := 32
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);
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port(
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-- [..Q1,I1,Q0,I0] (I in LSBs). Each I and Q data is 16 bits wide, but
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-- since the data is only 1/2 full scale. Useful information is only
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-- in the lower 15 bits, with upper two bits used as a signed bit.
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cDataIn : in std_logic_vector(kDataWidth-1 downto 0);
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cDataValidIn : in std_logic;
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-- [..Q1,I1,Q0,I0] (I in LSBs). 16 bit output with a gain of 2x.
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cDataOut : out std_logic_vector(kDataWidth-1 downto 0);
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cDataValidOut : out std_logic
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);
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end scale_2x;
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architecture RTL of scale_2x is
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begin
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-- Scale the date by 2 by shifting the data to the left by 1 bit.
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cDataOut <= Gain2x(cDataIn);
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cDataValidOut <= cDataValidIn;
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end RTL;
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