5cadf901c7
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
38 lines
1.6 KiB
Tcl
38 lines
1.6 KiB
Tcl
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# Clock definition constraints for X440
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#
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###############################################################################
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# MMCM-Related Clocks
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#
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# Note: Vivado will create generated clocks based on the default MMCM settings
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# configured in the clocking wizard, but we are going to dynamically change
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# those clocks, and so we need to provide worst-case values in here.
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###############################################################################
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# PLL Reference Clock (PRC) input. This goes from the LMK straight to the MMCM
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# input, and is used to generate the internal PRC as well as RFDC/data clocks.
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set pll_ref_clk_in_period 15.625
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create_clock -name pll_ref_in_clk -period $pll_ref_clk_in_period [get_ports PLL_REFCLK_FPGA_P]
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# Internal PLL Reference Clock (PRC). Used to derive data clocks. Constrain to
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# the fastest possible clock rate supported in the driver.
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set pll_ref_clk_period 15.625
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create_clock -name pll_ref_clk \
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-period $pll_ref_clk_period \
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[get_pins x440_ps_rfdc_bd_i/rfdc/data_clock_mmcm/inst/CLK_CORE_DRP_I/clk_inst/mmcme4_adv_inst/CLKOUT0]
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###############################################################################
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# Generated Clocks
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###############################################################################
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create_generated_clock -name sync_ref_clk \
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-source [get_ports BASE_REFCLK_FPGA_P] \
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-divide_by 2 [get_pins clock_div_5mhz/clk_out_reg/Q]
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