Wade Fife
dce6ce8063
This updates the makefiles for the testbenches so they can be run using "make modelsim" without any additional hacks. The "xsim" and "vsim" simulation targets also still work. Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
81 lines
2.7 KiB
Makefile
81 lines
2.7 KiB
Makefile
#
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# Copyright 2020 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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SYNTH_DUT = eth_ifc_synth_test
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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include $(BASE_DIR)/../lib/axi/Makefile.srcs
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include $(BASE_DIR)/../lib/axi4s_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/packet_proc/Makefile.srcs
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include $(BASE_DIR)/../lib/xge_interface/Makefile.srcs
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include $(BASE_DIR)/../lib/fifo/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/xport/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/xport_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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IP_DIR = $(BASE_DIR)/x300/ip
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include $(BASE_DIR)/x300/ip/fifo_short_2clk/Makefile.inc
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DESIGN_SRCS = $(abspath \
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eth_ifc_synth_test.sv \
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$(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) \
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$(AXI_SRCS) \
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$(AXI4S_SV_SRCS) \
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$(XGE_INTERFACE_SRCS) \
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$(PACKET_PROC_SRCS) \
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$(RFNOC_UTIL_SRCS) \
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$(RFNOC_XPORT_SRCS) \
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$(RFNOC_XPORT_SV_SRCS) \
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$(RFNOC_XBAR_SRCS) \
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$(RFNOC_CORE_SRCS) \
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$(IP_FIFO_SHORT_2CLK_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm fifo_generator_v13_2_4
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MODELSIM_ARGS += glbl -t 1fs
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# Define toplevel module
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TB_TOP_MODULE ?= eth_ifc_all_tb
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#TB_TOP_MODULE ?= eth_ifc_synth_test
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SIM_TOP = $(TB_TOP_MODULE)
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SIM_SRCS = \
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$(abspath $(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v) \
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$(abspath eth_ifc_tb.sv) \
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$(abspath $(TB_TOP_MODULE).sv) \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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# Suppressing the following worthless reminder.
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#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
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# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
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SVLOG_ARGS = -suppress 2583 -keep_delta
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VLOG_ARGS = -keep_delta
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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