86 lines
3.1 KiB
Systemverilog
86 lines
3.1 KiB
Systemverilog
//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_if_splitter
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//
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// Description:
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//
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// This block splits a single control-port interface into multiple. It is used
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// when you have a single master that needs to access multiple slaves. For
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// example, a NoC block where the registers are implemented in multiple
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// submodules that must be read/written by a single NoC shell.
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//
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// Note that this block does not do any address decoding, so the connected
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// slaves must use non-overlapping address spaces.
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//
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// This module takes the request received by its single slave interface and
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// outputs it on all its master interfaces. In the opposite direction, it takes
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// the responses received by its multiple master interfaces and combines them
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// into a single response on its slave interface. This is done by using the ack
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// bit of each response to mask the other bits of the response, then OR'ing all
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// of the masked responses together onto a single response bus. This is valid
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// because only one block is allowed to respond to a single request.
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//
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// Parameters:
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//
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// NUM_SLAVES : The number of slaves you want to connect to a master.
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//
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module ctrlport_if_splitter #(
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int NUM_SLAVES = 2
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) (
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// Slave Interface
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ctrlport_if.slave s_ctrlport,
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// Master Interfaces
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ctrlport_if.master m_ctrlport [NUM_SLAVES-1:0]
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);
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import ctrlport_pkg::*;
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generate
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if (NUM_SLAVES == 1) begin : gen_no_split
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assign m_ctrlport[0].req = s_ctrlport.req;
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assign s_ctrlport.resp = m_ctrlport[0].resp;
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end else begin : gen_splitter
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//---------------------------------------------------------------------------
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// Split the requests among the slaves
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//---------------------------------------------------------------------------
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for (genvar i = 0; i < NUM_SLAVES; i++) begin : gen_split
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// No special logic is required to split the requests from the master among
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// multiple slaves.
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assign m_ctrlport[i].req = s_ctrlport.req;
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end
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//---------------------------------------------------------------------------
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// Decode the responses
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//---------------------------------------------------------------------------
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// Take the responses and mask them with their respective ack
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ctrlport_response_t masked_resp [NUM_SLAVES-1:0];
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for (genvar i = 0; i < NUM_SLAVES; i++) begin : gen_mask
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assign masked_resp[i] = m_ctrlport[i].resp.ack ? m_ctrlport[i].resp : '0;
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end
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// Combine the masked responses by OR'ing them together
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ctrlport_response_t combined_resp;
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always_comb begin : response_combine
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combined_resp = '0;
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for (int i = 0; i < NUM_SLAVES; i++) begin : gen_or
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combined_resp = combined_resp | masked_resp[i];
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end
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end
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// Register the output to break combinatorial path
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always_ff @(posedge s_ctrlport.clk) begin : response_reg
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s_ctrlport.resp <= combined_resp;
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if (s_ctrlport.rst) begin
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s_ctrlport.resp.ack <= '0;
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end
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end
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end
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endgenerate
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endmodule
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