Wade Fife
c322899053
This adds DRAM support to E31x devices. Due to the size of the DDR3 memory controller, it is not enabled by default. You can include the memory controller IP in the build by adding the DRAM environment variable to your build. For example: DRAM=1 make E310_SG3 Original-commit: 788fef11ef890c6dcee3be495fc381bcf2990d3b
33 lines
1.3 KiB
Makefile
33 lines
1.3 KiB
Makefile
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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IP_DDR3_16BIT_SRCS = $(IP_BUILD_DIR)/ddr3_16bit/ddr3_16bit.xci
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IP_DDR3_16BIT_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \
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ddr3_16bit.xci.out \
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ddr3_16bit/user_design/rtl/ddr3_16bit.v \
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ddr3_16bit/user_design/rtl/ddr3_16bit_mig.v \
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)
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IP_MIG_7SERIES_TG_SRCS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \
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ddr3_16bit/example_design/rtl/example_top.v \
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ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_tg.v \
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ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_axi4_wrapper.v \
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ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_cmd_prbs_gen_axi.v \
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ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_data_gen_chk.v \
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ddr3_16bit/example_design/rtl/traffic_gen/mig_7series_v4_2_tg.v \
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)
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IP_DDR3_16BIT_SIM_OUTS = $(addprefix $(IP_BUILD_DIR)/ddr3_16bit/, \
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ddr3_16bit/example_design/sim/ddr3_model.sv \
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ddr3_16bit/example_design/sim/ddr3_model_parameters.vh \
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)
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$(IP_DDR3_16BIT_SRCS) $(IP_DDR3_16BIT_OUTS) : $(IP_DIR)/ddr3_16bit/ddr3_16bit.xci $(IP_DIR)/ddr3_16bit/mig_*.prj
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cp -f $(IP_DIR)/ddr3_16bit/mig_$(subst /,,$(PART_ID)).prj $(IP_DIR)/ddr3_16bit/mig_a.prj # Note: This won't allow parallel IP builds
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$(call BUILD_VIVADO_IP,ddr3_16bit,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
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rm -f $(IP_DIR)/ddr3_16bit/mig_a.prj
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