531 lines
22 KiB
Verilog
531 lines
22 KiB
Verilog
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// radio top level module
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// Contains all clock-rate DSP components, all radio and hardware controls and settings
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// Communication with outside world is exclusively via a single in/out axi cvita port
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// Paths are separated by the lower 2 bits of stream ID, as follows:
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//
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// SID[1:0] IN OUT
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// 0 Transmit Data (DATA) Transmit Flow Control, ACK/Error (CTXT)
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// 1 Control (SPI, settings) (CTXT) Response (readback) (CTXT)
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// 2 Receive Flow Control (CTXT) Receive Data (DATA)
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// 3 Receive Commands (CTXT) Receive Command ACK/ERROR (CTXT)
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module radio
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#(
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parameter CHIPSCOPE = 0,
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parameter DELETE_DSP = 0
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)
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(input radio_clk, input radio_rst,
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input [31:0] rx, output [31:0] tx,
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inout [31:0] db_gpio,
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inout [31:0] fp_gpio,
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output [7:0] sen, output sclk, output mosi, input miso,
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output [7:0] misc_outs, output [2:0] leds,
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input bus_clk, input bus_rst,
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input [63:0] in_tdata, input in_tlast, input in_tvalid, output in_tready,
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output [63:0] out_tdata, output out_tlast, output out_tvalid, input out_tready,
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input [63:0] tx_tdata_bi, input tx_tlast_bi, input tx_tvalid_bi, output tx_tready_bi,
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output [63:0] tx_tdata_bo, output tx_tlast_bo, output tx_tvalid_bo, input tx_tready_bo,
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input pps,
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output sync_dacs,
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output [31:0] debug
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);
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// ///////////////////////////////////////////////////////////////////////////////
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// FIFO Interfacing to the bus clk domain
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// in_tdata splits to tx_tdata and ctrl_tdata
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// rx_tdata and resp_tdata get muxed to out_tdata
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// Everything except rx flow control must cross in to radio_clk domain before further use
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// _b signifies bus_clk domain, _r signifies radio_clk domain, _b_fc is bus_clk domain, post flow control
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wire [63:0] ctrl_tdata_b, ctrl_tdata_r;
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wire ctrl_tready_b, ctrl_tready_r, ctrl_tvalid_b, ctrl_tvalid_r;
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wire ctrl_tlast_b, ctrl_tlast_r;
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wire [63:0] ctrl_tdata_s_r;
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wire ctrl_tready_s_r, ctrl_tvalid_s_r;
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wire ctrl_tlast_s_r;
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wire [63:0] resp_tdata_b, resp_tdata_r;
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wire resp_tready_b, resp_tready_r, resp_tvalid_b, resp_tvalid_r;
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wire resp_tlast_b, resp_tlast_r;
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wire [63:0] rx_tdata_b, rx_tdata_b_fc, rx_tdata_r;
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wire rx_tready_b, rx_tready_b_fc, rx_tready_r, rx_tvalid_b, rx_tvalid_b_fc, rx_tvalid_r;
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wire rx_tlast_b, rx_tlast_b_fc, rx_tlast_r;
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// IJB. _b signals now unused since adding DRAM FIFO.
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wire [63:0] tx_tdata_b, tx_tdata_r;
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wire tx_tready_b, tx_tready_r, tx_tvalid_b, tx_tvalid_r;
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wire tx_tlast_b, tx_tlast_r;
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wire [63:0] txresp_tdata_b, txresp_tdata_r;
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wire txresp_tready_b, txresp_tready_r, txresp_tvalid_b, txresp_tvalid_r;
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wire txresp_tlast_b, txresp_tlast_r;
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wire [63:0] rxfc_tdata_b;
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wire rxfc_tready_b, rxfc_tvalid_b, rxfc_tlast_b;
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wire [63:0] rx_mux_tdata_r;
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wire rx_mux_tready_r, rx_mux_tvalid_r;
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wire rx_mux_tlast_r;
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wire [63:0] rx_err_tdata_r;
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wire rx_err_tready_r, rx_err_tvalid_r;
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wire rx_err_tlast_r;
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//IJB debug
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wire [63:0] tx_tdata_bo_debug;
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wire tx_tlast_bo_debug, tx_tvalid_bo_debug, tx_tready_bo_debug;
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axi_mux4 #(.PRIO(0), .WIDTH(64), .BUFFER(1)) radio_mux
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(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
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.i0_tdata(txresp_tdata_b), .i0_tlast(txresp_tlast_b), .i0_tvalid(txresp_tvalid_b), .i0_tready(txresp_tready_b), // TX Flow Control/ACK
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.i1_tdata(resp_tdata_b), .i1_tlast(resp_tlast_b), .i1_tvalid(resp_tvalid_b), .i1_tready(resp_tready_b), // Control Response
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.i2_tdata(rx_tdata_b_fc), .i2_tlast(rx_tlast_b_fc), .i2_tvalid(rx_tvalid_b_fc), .i2_tready(rx_tready_b_fc), // RX Data
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.i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(), // RX Command ACK/ERR
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.o_tdata(out_tdata), .o_tlast(out_tlast), .o_tvalid(out_tvalid), .o_tready(out_tready));
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wire [63:0] vheader;
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wire [1:0] vdest = vheader[1:0]; // Switch by bottom 2 bits of SID
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axi_demux4 #(.ACTIVE_CHAN(4'b0111), .WIDTH(64)) radio_demux
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(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
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.header(vheader), .dest(vdest),
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.i_tdata(in_tdata), .i_tlast(in_tlast), .i_tvalid(in_tvalid), .i_tready(in_tready),
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.o0_tdata(tx_tdata_bo), .o0_tlast(tx_tlast_bo), .o0_tvalid(tx_tvalid_bo), .o0_tready(tx_tready_bo), // TX Data
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.o1_tdata(ctrl_tdata_b), .o1_tlast(ctrl_tlast_b), .o1_tvalid(ctrl_tvalid_b), .o1_tready(ctrl_tready_b), // Control
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.o2_tdata(rxfc_tdata_b), .o2_tlast(rxfc_tlast_b), .o2_tvalid(rxfc_tvalid_b), .o2_tready(rxfc_tready_b), // RX Flow Control
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.o3_tdata(), .o3_tlast(), .o3_tvalid(), .o3_tready(1'b1)); // RX Command
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axi_fifo_2clk #(.WIDTH(65), .SIZE(9)) ctrl_fifo
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(.reset(bus_rst),
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.i_aclk(bus_clk), .i_tvalid(ctrl_tvalid_b), .i_tready(ctrl_tready_b), .i_tdata({ctrl_tlast_b,ctrl_tdata_b}),
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.o_aclk(radio_clk), .o_tvalid(ctrl_tvalid_s_r), .o_tready(ctrl_tready_s_r), .o_tdata({ctrl_tlast_s_r,ctrl_tdata_s_r}));
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// For timing closure ..paths lead back from 64bit time comparison.
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axi_fifo_short #(.WIDTH(65)) ctrl_fifo_s
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(
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.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
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.i_tdata({ctrl_tlast_s_r,ctrl_tdata_s_r}), .i_tvalid(ctrl_tvalid_s_r), .i_tready(ctrl_tready_s_r),
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.o_tdata({ctrl_tlast_r,ctrl_tdata_r}), .o_tvalid(ctrl_tvalid_r), .o_tready(ctrl_tready_r),
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.space(), .occupied()
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);
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axi_fifo_2clk #(.WIDTH(65), .SIZE(13)) tx_fifo
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(.reset(bus_rst),
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.i_aclk(bus_clk), .i_tvalid(tx_tvalid_bi), .i_tready(tx_tready_bi), .i_tdata({tx_tlast_bi,tx_tdata_bi}),
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.o_aclk(radio_clk), .o_tvalid(tx_tvalid_r), .o_tready(tx_tready_r), .o_tdata({tx_tlast_r,tx_tdata_r}));
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axi_fifo_2clk #(.WIDTH(65), .SIZE(9)) resp_fifo
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(.reset(radio_rst),
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.i_aclk(radio_clk), .i_tvalid(resp_tvalid_r), .i_tready(resp_tready_r), .i_tdata({resp_tlast_r,resp_tdata_r}),
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.o_aclk(bus_clk), .o_tvalid(resp_tvalid_b), .o_tready(resp_tready_b), .o_tdata({resp_tlast_b,resp_tdata_b}));
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axi_fifo_2clk #(.WIDTH(65), .SIZE(10)) rx_fifo
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(.reset(radio_rst),
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.i_aclk(radio_clk), .i_tvalid(rx_mux_tvalid_r), .i_tready(rx_mux_tready_r), .i_tdata({rx_mux_tlast_r,rx_mux_tdata_r}),
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.o_aclk(bus_clk), .o_tvalid(rx_tvalid_b), .o_tready(rx_tready_b), .o_tdata({rx_tlast_b,rx_tdata_b}));
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axi_fifo_2clk #(.WIDTH(65), .SIZE(9)) txresp_fifo
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(.reset(radio_rst),
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.i_aclk(radio_clk), .i_tvalid(txresp_tvalid_r), .i_tready(txresp_tready_r), .i_tdata({txresp_tlast_r,txresp_tdata_r}),
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.o_aclk(bus_clk), .o_tvalid(txresp_tvalid_b), .o_tready(txresp_tready_b), .o_tdata({txresp_tlast_b,txresp_tdata_b}));
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// /////////////////////////////////////////////////////////////////////////////////////
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// Setting bus and controls
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localparam SR_DACSYNC = 8'd5;
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localparam SR_LOOPBACK = 8'd6;
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localparam SR_TEST = 8'd7;
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localparam SR_SPI = 8'd8;
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localparam SR_GPIO = 8'd16;
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localparam SR_MISC_OUTS = 8'd24;
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localparam SR_READBACK = 8'd32;
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localparam SR_TX_CTRL = 8'd64;
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localparam SR_RX_CTRL = 8'd96;
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localparam SR_TIME = 8'd128;
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localparam SR_RX_DSP = 8'd144;
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localparam SR_TX_DSP = 8'd184;
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localparam SR_LEDS = 8'd196;
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localparam SR_FP_GPIO = 8'd200;
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localparam SR_RX_FRONT = 8'd208;
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localparam SR_TX_FRONT = 8'd216;
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wire set_stb;
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wire [7:0] set_addr;
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wire [31:0] set_data;
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wire set_stb_b;
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wire [7:0] set_addr_b;
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wire [31:0] set_data_b;
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wire [31:0] fp_gpio_readback, gpio_readback, spi_readback;
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wire run_rx, run_tx;
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wire strobe_tx;
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wire spi_ready;
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reg [63:0] rb_data;
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wire [2:0] rb_addr;
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wire [63:0] vita_time, vita_time_lastpps;
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wire [31:0] test_readback;
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wire loopback;
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radio_ctrl_proc radio_ctrl_proc
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(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
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.ctrl_tdata(ctrl_tdata_r), .ctrl_tlast(ctrl_tlast_r), .ctrl_tvalid(ctrl_tvalid_r), .ctrl_tready(ctrl_tready_r),
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.resp_tdata(resp_tdata_r), .resp_tlast(resp_tlast_r), .resp_tvalid(resp_tvalid_r), .resp_tready(resp_tready_r),
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.vita_time(vita_time),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.ready(spi_ready), .readback(rb_data),
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.debug());
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// Radio Readback Mux
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always @*
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case(rb_addr)
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3'd0 : rb_data <= { spi_readback, gpio_readback};
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3'd1 : rb_data <= vita_time;
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3'd2 : rb_data <= vita_time_lastpps;
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3'd3 : rb_data <= {rx, test_readback};
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3'd4 : rb_data <= {32'b0, fp_gpio_readback};
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default : rb_data <= 64'd0;
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endcase // case (rb_addr)
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settings_bus_crossclock
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#(.FLOW_CTRL(0))
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settings_bus_crossclock
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(.clk_i(radio_clk), .rst_i(radio_rst),
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.set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data),
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.clk_o(bus_clk), .rst_o(bus_rst),
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.set_stb_o(set_stb_b), .set_addr_o(set_addr_b), .set_data_o(set_data_b),
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.blocked(1'b0));
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// Write this register with any value to create DAC sync operation
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setting_reg #(.my_addr(SR_DACSYNC), .awidth(8), .width(1)) sr_dacsync
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(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(), .changed(sync_dacs));
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// Set this register to loop TX data directly to RX data.
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setting_reg #(.my_addr(SR_LOOPBACK), .awidth(8), .width(1)) sr_loopback
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(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(loopback), .changed());
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// Set this register to put a test value on the readback mux.
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setting_reg #(.my_addr(SR_TEST), .awidth(8), .width(32)) sr_test
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(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(test_readback), .changed());
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setting_reg #(.my_addr(SR_READBACK), .awidth(8), .width(3)) sr_rdback
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(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(rb_addr), .changed());
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setting_reg #(.my_addr(SR_MISC_OUTS), .awidth(8), .width(8), .at_reset(8'h0)) sr_misc
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(.clk(radio_clk), .rst(radio_rst), .strobe(set_stb), .addr(set_addr), .in(set_data),
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.out(misc_outs), .changed());
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simple_spi_core #(.BASE(SR_SPI), .WIDTH(8), .CLK_IDLE(0), .SEN_IDLE(8'hFF)) radio_spi
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(.clock(radio_clk), .reset(radio_rst),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.readback(spi_readback), .ready(spi_ready),
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.sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso),
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.debug());
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gpio_atr #(.BASE(SR_GPIO), .WIDTH(32)) gpio_atr
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(.clk(radio_clk),.reset(radio_rst),
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.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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.rx(run_rx), .tx(run_tx),
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.gpio(db_gpio), .gpio_readback(gpio_readback) );
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gpio_atr #(.BASE(SR_FP_GPIO), .WIDTH(32)) fp_gpio_atr
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(.clk(radio_clk),.reset(radio_rst),
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.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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.rx(run_rx), .tx(run_tx),
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.gpio(fp_gpio), .gpio_readback(fp_gpio_readback) );
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gpio_atr #(.BASE(SR_LEDS), .WIDTH(3), .default_ddr(3'b111), .default_idle(3'b000)) gpio_leds
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(.clk(radio_clk),.reset(radio_rst),
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.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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.rx(run_rx), .tx(run_tx),
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.gpio(leds), .gpio_readback() );
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timekeeper #(.BASE(SR_TIME)) timekeeper
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(.clk(radio_clk), .reset(radio_rst), .pps(pps),
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.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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.vita_time(vita_time), .vita_time_lastpps(vita_time_lastpps));
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// /////////////////////////////////////////////////////////////////////////////////
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// TX Chain
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wire [175:0] txsample_tdata;
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wire txsample_tvalid, txsample_tready;
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wire [31:0] sample_tx;
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wire ack_or_error, packet_consumed;
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wire [11:0] seqnum;
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wire [63:0] error_code;
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wire [31:0] sid;
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wire [23:0] tx_fe_i, tx_fe_q;
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new_tx_deframer tx_deframer
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(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
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.i_tdata(tx_tdata_r), .i_tlast(tx_tlast_r), .i_tvalid(tx_tvalid_r), .i_tready(tx_tready_r),
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.sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready));
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new_tx_control #(.BASE(SR_TX_CTRL)) tx_control
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(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.vita_time(vita_time),
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.ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
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.seqnum(seqnum), .error_code(error_code), .sid(sid),
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.sample_tdata(txsample_tdata), .sample_tvalid(txsample_tvalid), .sample_tready(txsample_tready),
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.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
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.debug());
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tx_responder #(.BASE(SR_TX_CTRL+2)) tx_responder
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(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.ack_or_error(ack_or_error), .packet_consumed(packet_consumed),
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.seqnum(seqnum), .error_code(error_code), .sid(sid),
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.vita_time(vita_time),
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.o_tdata(txresp_tdata_r), .o_tlast(txresp_tlast_r), .o_tvalid(txresp_tvalid_r), .o_tready(txresp_tready_r));
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generate
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if (DELETE_DSP==0) begin: tx_dsp
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duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0), .WIDTH(24)) duc_chain
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(.clk(radio_clk), .rst(radio_rst), .clr(1'b0),
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.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
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.tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
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.sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
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.debug() );
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tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(16), .IQCOMP_EN(1)) tx_frontend
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(.clk(radio_clk), .rst(radio_rst),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(run_tx),
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.dac_a(tx[31:16]), .dac_b(tx[15:0]));
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end
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endgenerate
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// /////////////////////////////////////////////////////////////////////////////////
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// RX Chain
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wire full, eob_rx;
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wire strobe_rx;
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wire [31:0] sample_rx;
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wire [31:0] rx_sid;
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wire [11:0] rx_seqnum;
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source_flow_control #(.BASE(SR_RX_CTRL+6)) rx_sfc
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(.clk(bus_clk), .reset(bus_rst), .clear(1'b0),
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.set_stb(set_stb_b), .set_addr(set_addr_b), .set_data(set_data_b),
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.fc_tdata(rxfc_tdata_b), .fc_tlast(rxfc_tlast_b), .fc_tvalid(rxfc_tvalid_b), .fc_tready(rxfc_tready_b),
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.in_tdata(rx_tdata_b), .in_tlast(rx_tlast_b), .in_tvalid(rx_tvalid_b), .in_tready(rx_tready_b),
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.out_tdata(rx_tdata_b_fc), .out_tlast(rx_tlast_b_fc), .out_tvalid(rx_tvalid_b_fc), .out_tready(rx_tready_b_fc) );
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new_rx_framer #(.BASE(SR_RX_CTRL+4),.CHIPSCOPE(CHIPSCOPE)) new_rx_framer
|
|
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
|
|
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
|
.vita_time(vita_time),
|
|
.strobe(strobe_rx), .sample(sample_rx), .run(run_rx), .eob(eob_rx), .full(full),
|
|
.sid(rx_sid), .seqnum(rx_seqnum),
|
|
.o_tdata(rx_tdata_r), .o_tlast(rx_tlast_r), .o_tvalid(rx_tvalid_r), .o_tready(rx_tready_r),
|
|
.debug());
|
|
|
|
new_rx_control #(.BASE(SR_RX_CTRL)) new_rx_control
|
|
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
|
|
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
|
|
.vita_time(vita_time),
|
|
.strobe(strobe_rx), .run(run_rx), .eob(eob_rx), .full(full),
|
|
.sid(rx_sid), .seqnum(rx_seqnum),
|
|
.err_tdata(rx_err_tdata_r), .err_tlast(rx_err_tlast_r), .err_tvalid(rx_err_tvalid_r), .err_tready(rx_err_tready_r),
|
|
.debug());
|
|
|
|
wire [23:0] rx_corr_i, rx_corr_q;
|
|
|
|
// Digital Loopback TX -> RX (Pipeline immediately inside rx_frontend).
|
|
wire [31:0] rx_fe = loopback ? tx : rx;
|
|
|
|
generate
|
|
if (DELETE_DSP==0)
|
|
begin: rx_dsp
|
|
rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
|
|
(.clk(radio_clk),.rst(radio_rst),
|
|
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
|
|
.adc_a(rx_fe[31:16]),.adc_ovf_a(1'b0),
|
|
.adc_b(rx_fe[15:0]),.adc_ovf_b(1'b0),
|
|
.i_out(rx_corr_i), .q_out(rx_corr_q),
|
|
.run(run_rx0_d1 | run_rx1_d1), .debug());
|
|
|
|
ddc_chain_x300 #(.BASE(SR_RX_DSP), .DSPNO(0), .WIDTH(24)) ddc_chain
|
|
(.clk(radio_clk), .rst(radio_rst), .clr(1'b0),
|
|
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
|
|
.rx_fe_i(rx_corr_i),.rx_fe_q(rx_corr_q),
|
|
.sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
|
|
.debug() );
|
|
end
|
|
endgenerate
|
|
|
|
// /////////////////////////////////////////////////////////////////////////////////
|
|
// RX Channel Muxing
|
|
|
|
axi_mux4 #(.PRIO(1), .WIDTH(64)) rx_mux
|
|
(.clk(radio_clk), .reset(radio_rst), .clear(1'b0),
|
|
.i0_tdata(rx_tdata_r), .i0_tlast(rx_tlast_r), .i0_tvalid(rx_tvalid_r), .i0_tready(rx_tready_r),
|
|
.i1_tdata(rx_err_tdata_r), .i1_tlast(rx_err_tlast_r), .i1_tvalid(rx_err_tvalid_r), .i1_tready(rx_err_tready_r),
|
|
.i2_tdata(), .i2_tlast(), .i2_tvalid(1'b0), .i2_tready(),
|
|
.i3_tdata(), .i3_tlast(), .i3_tvalid(1'b0), .i3_tready(),
|
|
.o_tdata(rx_mux_tdata_r), .o_tlast(rx_mux_tlast_r), .o_tvalid(rx_mux_tvalid_r), .o_tready(rx_mux_tready_r));
|
|
|
|
// /////////////////////////////////////////////////////////////////////////////////
|
|
// Debug
|
|
/* -----\/----- EXCLUDED -----\/-----
|
|
generate
|
|
if (CHIPSCOPE) begin: chipscope_gen
|
|
|
|
(* keep = "true", max_fanout = 10 *) reg debug_set_stb;
|
|
(* keep = "true", max_fanout = 10 *) reg [7:0] debug_set_addr;
|
|
(* keep = "true", max_fanout = 10 *) reg [31:0] debug_set_data;
|
|
(* keep = "true", max_fanout = 10 *) reg [63:0] debug_ctrl_tdata_r;
|
|
(* keep = "true", max_fanout = 10 *) reg debug_ctrl_tlast_r;
|
|
(* keep = "true", max_fanout = 10 *) reg debug_ctrl_tvalid_r;
|
|
(* keep = "true", max_fanout = 10 *) reg debug_ctrl_tready_r;
|
|
|
|
|
|
always @(posedge radio_clk) begin
|
|
debug_set_stb <= set_stb;
|
|
debug_set_addr <= set_addr[7:0];
|
|
debug_set_data <= set_data[31:0];
|
|
debug_ctrl_tdata_r <= ctrl_tdata_r;
|
|
debug_ctrl_tlast_r <= ctrl_tlast_r;
|
|
debug_ctrl_tvalid_r <= ctrl_tvalid_r;
|
|
debug_ctrl_tready_r <= ctrl_tready_r;
|
|
end
|
|
|
|
|
|
wire [35:0] CONTROL0;
|
|
wire [63:0] TRIG0;
|
|
|
|
assign TRIG0 = {
|
|
sync_dacs, // 109
|
|
loopback, // 108
|
|
debug_ctrl_tready_r, // 107
|
|
debug_ctrl_tvalid_r, // 106
|
|
debug_ctrl_tlast_r, // 105
|
|
debug_ctrl_tdata_r, // 104:41
|
|
debug_set_stb, // 40
|
|
debug_set_addr, // 39:32
|
|
debug_set_data // 31:0
|
|
};
|
|
|
|
|
|
chipscope_ila chipscope_ila_i0
|
|
(
|
|
.CONTROL(CONTROL0), // INOUT BUS [35:0]
|
|
.CLK(radio_clk), // IN
|
|
.TRIG0(TRIG0 ) // IN BUS [255:0]
|
|
);
|
|
|
|
chipscope_icon chipscope_icon_i0
|
|
(
|
|
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
|
|
);
|
|
|
|
end // block: chipscope
|
|
endgenerate
|
|
-----/\----- EXCLUDED -----/\----- */
|
|
|
|
/* -----\/----- EXCLUDED -----\/-----
|
|
|
|
generate
|
|
if (CHIPSCOPE) begin: chipscope_gen
|
|
(* keep = "true", max_fanout = 10 *) reg [5:0] debug_error_code; // 174:169
|
|
(* keep = "true", max_fanout = 10 *) reg debug_ack_or_error; // 168
|
|
(* keep = "true", max_fanout = 10 *) reg debug_run_rx; // 167
|
|
(* keep = "true", max_fanout = 10 *) reg debug_strobe_rx; // 166
|
|
(* keep = "true", max_fanout = 10 *) reg debug_rx_err_tvalid_r; // 165
|
|
(* keep = "true", max_fanout = 10 *) reg debug_rx_err_tready_r; // 164
|
|
(* keep = "true", max_fanout = 10 *) reg debug_rx_err_tlast_r; // 163
|
|
(* keep = "true", max_fanout = 10 *) reg debug_rx_tvalid_r; // 162
|
|
(* keep = "true", max_fanout = 10 *) reg debug_rx_tready_r; // 161
|
|
(* keep = "true", max_fanout = 10 *) reg debug_rx_tlast_r; // 160
|
|
(* keep = "true", max_fanout = 10 *) reg [31:0] debug_sample_rx; // 159:128
|
|
(* keep = "true", max_fanout = 10 *) reg [63:0] debug_rx_err_tdata_r; // 127:64
|
|
(* keep = "true", max_fanout = 10 *) reg [63:0] debug_rx_tdata_r; // 63:0
|
|
(* keep = "true", max_fanout = 10 *) reg debug_set_stb;
|
|
(* keep = "true", max_fanout = 10 *) reg [7:0] debug_set_addr;
|
|
(* keep = "true", max_fanout = 10 *) reg [7:0] debug_set_data;
|
|
(* keep = "true", max_fanout = 10 *) reg [63:0] debug_tx_tdata_r;
|
|
(* keep = "true", max_fanout = 10 *) reg debug_tx_tlast_r;
|
|
(* keep = "true", max_fanout = 10 *) reg debug_tx_tvalid_r;
|
|
(* keep = "true", max_fanout = 10 *) reg debug_tx_tready_r;
|
|
(* keep = "true", max_fanout = 10 *) reg [11:0] debug_seq_id;
|
|
(* keep = "true", max_fanout = 10 *) reg debug_run_tx;
|
|
(* keep = "true", max_fanout = 10 *) reg debug_strobe_tx;
|
|
|
|
|
|
always @(posedge radio_clk) begin
|
|
debug_set_stb <= set_stb;
|
|
debug_set_addr <= set_addr;
|
|
debug_set_data <= set_data[7:0];
|
|
debug_error_code <= error_code[37:32];
|
|
debug_ack_or_error <= ack_or_error;
|
|
debug_run_rx <= run_rx ;
|
|
debug_strobe_rx <= strobe_rx;
|
|
debug_rx_err_tvalid_r <= rx_err_tvalid_r;
|
|
debug_rx_err_tready_r <= rx_err_tready_r;
|
|
debug_rx_err_tlast_r <= rx_err_tlast_r;
|
|
debug_rx_tvalid_r <= rx_tvalid_r ;
|
|
debug_rx_tready_r <= rx_tready_r;
|
|
debug_rx_tlast_r <= rx_tlast_r;
|
|
debug_sample_rx[31:0] <= sample_rx[31:0];
|
|
debug_rx_err_tdata_r[63:0] <= rx_err_tdata_r[63:0];
|
|
debug_rx_tdata_r[63:0] <= rx_tdata_r[63:0];
|
|
debug_tx_tdata_r <= tx_tdata_r;
|
|
debug_tx_tlast_r <= tx_tlast_r;
|
|
debug_tx_tvalid_r <= tx_tvalid_r;
|
|
debug_tx_tready_r <= tx_tready_r;
|
|
debug_seq_id <= error_code[11:0];
|
|
debug_ack_or_error <= ack_or_error;
|
|
debug_run_tx <= run_tx;
|
|
debug_strobe_tx <= strobe_tx;
|
|
|
|
end // always @ (posedge radio_clk)
|
|
|
|
wire [35:0] CONTROL0;
|
|
wire [255:0] TRIG0;
|
|
|
|
assign TRIG0 = {
|
|
debug_strobe_tx, // 87
|
|
debug_run_tx, // 86
|
|
debug_ack_or_error, // 85
|
|
debug_error_code[5:0], // 84:79
|
|
debug_seq_id[11:0], // 78:67
|
|
debug_tx_tready_r, // 66
|
|
debug_tx_tvalid_r, // 65
|
|
debug_tx_tlast_r, // 64
|
|
debug_tx_tdata_r[63:0] // 63:0
|
|
};
|
|
|
|
|
|
chipscope_ila chipscope_ila_i0
|
|
(
|
|
.CONTROL(CONTROL0), // INOUT BUS [35:0]
|
|
.CLK(radio_clk), // IN
|
|
.TRIG0(TRIG0 ) // IN BUS [255:0]
|
|
);
|
|
|
|
chipscope_icon chipscope_icon_i0
|
|
(
|
|
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
|
|
);
|
|
|
|
end // block: chipscope
|
|
endgenerate
|
|
-----/\----- EXCLUDED -----/\----- */
|
|
|
|
|
|
|
|
endmodule // radio
|