79 lines
4.4 KiB
Verilog
79 lines
4.4 KiB
Verilog
/*******************************************************************************
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* This file is owned and controlled by Xilinx and must be used solely *
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* for design, simulation, implementation and creation of design files *
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* limited to Xilinx devices or technologies. Use with non-Xilinx *
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* devices or technologies is expressly prohibited and immediately *
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* terminates your license. *
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* *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
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* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
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* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
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* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
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* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
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* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
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* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
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* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
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* PARTICULAR PURPOSE. *
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* *
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* Xilinx products are not intended for use in life support appliances, *
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* devices, or systems. Use in such applications are expressly *
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* prohibited. *
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* *
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* (c) Copyright 1995-2013 Xilinx, Inc. *
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* All rights reserved. *
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*******************************************************************************/
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/*******************************************************************************
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* Generated from core with identifier: xilinx.com:ip:fifo_generator:9.3 *
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* *
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* Rev 1. The FIFO Generator is a parameterizable first-in/first-out *
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* memory queue generator. Use it to generate resource and performance *
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* optimized FIFOs with common or independent read/write clock domains, *
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* and optional fixed or programmable full and empty flags and *
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* handshaking signals. Choose from a selection of memory resource *
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* types for implementation. Optional Hamming code based error *
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* detection and correction as well as error injection capability for *
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* system test help to insure data integrity. FIFO width and depth are *
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* parameterizable, and for native interface FIFOs, asymmetric read and *
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* write port widths are also supported. *
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*******************************************************************************/
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// Interfaces:
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// AXI4Stream_MASTER_M_AXIS
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// AXI4Stream_SLAVE_S_AXIS
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// AXI4_MASTER_M_AXI
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// AXI4_SLAVE_S_AXI
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// AXI4Lite_MASTER_M_AXI
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// AXI4Lite_SLAVE_S_AXI
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// master_aclk
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// slave_aclk
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// slave_aresetn
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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input_sample_fifo your_instance_name (
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.rst(rst), // input rst
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.wr_clk(wr_clk), // input wr_clk
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.rd_clk(rd_clk), // input rd_clk
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.din(din), // input [27 : 0] din
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.wr_en(wr_en), // input wr_en
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.rd_en(rd_en), // input rd_en
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.dout(dout), // output [27 : 0] dout
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.full(full), // output full
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.empty(empty), // output empty
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.almost_empty(almost_empty) // output almost_empty
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);
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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// You must compile the wrapper file input_sample_fifo.v when simulating
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// the core, input_sample_fifo. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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