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b210-k7-fpga/top/x300/coregen/coregen.cgp
T
Ben Hilburn fbbc991a7d Pushing the bulk of UHD-3.7.0 code.
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00

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SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc7k325t
SET devicefamily = kintex7
SET flowvendor = Foundation_ISE
SET package = ffg900
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false