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b210-k7-fpga/top/x300/coregen/chipscope_ila_64.ucf
T
Ben Hilburn fbbc991a7d Pushing the bulk of UHD-3.7.0 code.
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00

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#
# Clock constraints
#
NET "CLK" TNM_NET = D_CLK ;
INST "U0/*/U_STAT/U_DIRTY_LDC" TNM = D2_CLK;
TIMESPEC TS_D2_TO_T2_chipscope_ila_64 = FROM D2_CLK TO "FFS" TIG;
TIMESPEC TS_J2_TO_D2_chipscope_ila_64 = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J3_TO_D2_chipscope_ila_64 = FROM "FFS" TO D2_CLK TIG;
TIMESPEC TS_J4_TO_D2_chipscope_ila_64 = FROM "FFS" TO D2_CLK TIG;
#
# Input keep/save net constraints
#
NET "TRIG0<*" S;
NET "TRIG0<*" KEEP;