32 lines
906 B
Verilog
32 lines
906 B
Verilog
///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2013 Xilinx, Inc.
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// All Rights Reserved
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 14.4
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// \ \ Application: Xilinx CORE Generator
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// / / Filename : chipscope_ila.v
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// /___/ /\ Timestamp : Sun May 26 23:54:11 PDT 2013
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// \ \ / \
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// \___\/\___\
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//
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// Design Name: Verilog Synthesis Wrapper
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///////////////////////////////////////////////////////////////////////////////
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// This wrapper is used to integrate with Project Navigator and PlanAhead
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`timescale 1ns/1ps
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module chipscope_ila(
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CONTROL,
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CLK,
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TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
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inout [35 : 0] CONTROL;
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input CLK;
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input [255 : 0] TRIG0;
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endmodule
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