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b210-k7-fpga/top/x300/coregen/bootram/implement/implement.sh
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Ben Hilburn fbbc991a7d Pushing the bulk of UHD-3.7.0 code.
Original-commit: ff1546f8137f7f92bb250f685561b0c34cc0e053
2014-02-14 12:05:07 -08:00

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#!/bin/sh
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
cp bootram_exdes.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../bootram.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/bootram_exdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc7k410t-ffg900-2 bootram_exdes
echo 'Running map'
map bootram_exdes -o mapped.ncd -pr i
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed -g UnconstrainedPins:Allow
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm bootram_exdes -pcf mapped.pcf -w -sdf_anno false routed.ncd routed.v