124 lines
7.4 KiB
Verilog
124 lines
7.4 KiB
Verilog
/*******************************************************************************
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* This file is owned and controlled by Xilinx and must be used solely *
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* for design, simulation, implementation and creation of design files *
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* limited to Xilinx devices or technologies. Use with non-Xilinx *
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* devices or technologies is expressly prohibited and immediately *
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* terminates your license. *
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* *
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
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* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
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* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
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* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
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* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
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* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
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* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
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* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
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* PARTICULAR PURPOSE. *
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* *
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* Xilinx products are not intended for use in life support appliances, *
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* devices, or systems. Use in such applications are expressly *
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* prohibited. *
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* *
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* (c) Copyright 1995-2012 Xilinx, Inc. *
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* All rights reserved. *
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*******************************************************************************/
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/*******************************************************************************
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* Generated from core with identifier: xilinx.com:ip:axi_vfifo_ctrl:1.1 *
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* *
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* The AXI Virtual FIFO Controller is a parameterizable number of multi *
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* channel FIFO. *
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*******************************************************************************/
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// Interfaces:
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// AXI4Stream_MASTER_M_AXIS
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// AXI4Stream_SLAVE_S_AXIS
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// AXI4_MASTER_M_AXI
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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axi_vfifo_64 your_instance_name (
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.aclk(aclk), // input aclk
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.aresetn(aresetn), // input aresetn
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.m_axi_awid(m_axi_awid), // output [0 : 0] m_axi_awid
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.m_axi_awaddr(m_axi_awaddr), // output [31 : 0] m_axi_awaddr
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.m_axi_awlen(m_axi_awlen), // output [7 : 0] m_axi_awlen
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.m_axi_awsize(m_axi_awsize), // output [2 : 0] m_axi_awsize
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.m_axi_awburst(m_axi_awburst), // output [1 : 0] m_axi_awburst
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.m_axi_awlock(m_axi_awlock), // output [0 : 0] m_axi_awlock
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.m_axi_awcache(m_axi_awcache), // output [3 : 0] m_axi_awcache
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.m_axi_awprot(m_axi_awprot), // output [2 : 0] m_axi_awprot
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.m_axi_awqos(m_axi_awqos), // output [3 : 0] m_axi_awqos
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.m_axi_awregion(m_axi_awregion), // output [3 : 0] m_axi_awregion
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.m_axi_awuser(m_axi_awuser), // output [0 : 0] m_axi_awuser
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.m_axi_awvalid(m_axi_awvalid), // output m_axi_awvalid
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.m_axi_awready(m_axi_awready), // input m_axi_awready
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.m_axi_wdata(m_axi_wdata), // output [63 : 0] m_axi_wdata
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.m_axi_wstrb(m_axi_wstrb), // output [7 : 0] m_axi_wstrb
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.m_axi_wlast(m_axi_wlast), // output m_axi_wlast
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.m_axi_wuser(m_axi_wuser), // output [0 : 0] m_axi_wuser
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.m_axi_wvalid(m_axi_wvalid), // output m_axi_wvalid
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.m_axi_wready(m_axi_wready), // input m_axi_wready
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.m_axi_bid(m_axi_bid), // input [0 : 0] m_axi_bid
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.m_axi_bresp(m_axi_bresp), // input [1 : 0] m_axi_bresp
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.m_axi_buser(m_axi_buser), // input [0 : 0] m_axi_buser
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.m_axi_bvalid(m_axi_bvalid), // input m_axi_bvalid
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.m_axi_bready(m_axi_bready), // output m_axi_bready
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.m_axi_arid(m_axi_arid), // output [0 : 0] m_axi_arid
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.m_axi_araddr(m_axi_araddr), // output [31 : 0] m_axi_araddr
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.m_axi_arlen(m_axi_arlen), // output [7 : 0] m_axi_arlen
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.m_axi_arsize(m_axi_arsize), // output [2 : 0] m_axi_arsize
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.m_axi_arburst(m_axi_arburst), // output [1 : 0] m_axi_arburst
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.m_axi_arlock(m_axi_arlock), // output [0 : 0] m_axi_arlock
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.m_axi_arcache(m_axi_arcache), // output [3 : 0] m_axi_arcache
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.m_axi_arprot(m_axi_arprot), // output [2 : 0] m_axi_arprot
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.m_axi_arqos(m_axi_arqos), // output [3 : 0] m_axi_arqos
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.m_axi_arregion(m_axi_arregion), // output [3 : 0] m_axi_arregion
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.m_axi_aruser(m_axi_aruser), // output [0 : 0] m_axi_aruser
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.m_axi_arvalid(m_axi_arvalid), // output m_axi_arvalid
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.m_axi_arready(m_axi_arready), // input m_axi_arready
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.m_axi_rid(m_axi_rid), // input [0 : 0] m_axi_rid
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.m_axi_rdata(m_axi_rdata), // input [63 : 0] m_axi_rdata
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.m_axi_rresp(m_axi_rresp), // input [1 : 0] m_axi_rresp
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.m_axi_rlast(m_axi_rlast), // input m_axi_rlast
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.m_axi_ruser(m_axi_ruser), // input [0 : 0] m_axi_ruser
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.m_axi_rvalid(m_axi_rvalid), // input m_axi_rvalid
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.m_axi_rready(m_axi_rready), // output m_axi_rready
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.s_axis_tvalid(s_axis_tvalid), // input s_axis_tvalid
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.s_axis_tready(s_axis_tready), // output s_axis_tready
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.s_axis_tdata(s_axis_tdata), // input [63 : 0] s_axis_tdata
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.s_axis_tstrb(s_axis_tstrb), // input [7 : 0] s_axis_tstrb
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.s_axis_tkeep(s_axis_tkeep), // input [7 : 0] s_axis_tkeep
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.s_axis_tlast(s_axis_tlast), // input s_axis_tlast
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.s_axis_tid(s_axis_tid), // input [0 : 0] s_axis_tid
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.s_axis_tdest(s_axis_tdest), // input [0 : 0] s_axis_tdest
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.m_axis_tvalid(m_axis_tvalid), // output m_axis_tvalid
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.m_axis_tready(m_axis_tready), // input m_axis_tready
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.m_axis_tdata(m_axis_tdata), // output [63 : 0] m_axis_tdata
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.m_axis_tstrb(m_axis_tstrb), // output [7 : 0] m_axis_tstrb
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.m_axis_tkeep(m_axis_tkeep), // output [7 : 0] m_axis_tkeep
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.m_axis_tlast(m_axis_tlast), // output m_axis_tlast
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.m_axis_tid(m_axis_tid), // output [0 : 0] m_axis_tid
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.m_axis_tdest(m_axis_tdest), // output [0 : 0] m_axis_tdest
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.vfifo_mm2s_channel_full(vfifo_mm2s_channel_full), // input [1 : 0] vfifo_mm2s_channel_full
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.vfifo_s2mm_channel_full(vfifo_s2mm_channel_full), // output [1 : 0] vfifo_s2mm_channel_full
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.vfifo_mm2s_channel_empty(vfifo_mm2s_channel_empty), // output [1 : 0] vfifo_mm2s_channel_empty
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.vfifo_mm2s_rresp_err_intr(vfifo_mm2s_rresp_err_intr), // output vfifo_mm2s_rresp_err_intr
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.vfifo_s2mm_bresp_err_intr(vfifo_s2mm_bresp_err_intr), // output vfifo_s2mm_bresp_err_intr
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.vfifo_s2mm_overrun_err_intr(vfifo_s2mm_overrun_err_intr), // output vfifo_s2mm_overrun_err_intr
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.vfifo_idle(vfifo_idle) // output [1 : 0] vfifo_idle
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);
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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// You must compile the wrapper file axi_vfifo_64.v when simulating
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// the core, axi_vfifo_64. When compiling the wrapper file, be sure to
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// reference the XilinxCoreLib Verilog simulation library. For detailed
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// instructions, please refer to the "CORE Generator Help".
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