69 lines
1.5 KiB
Verilog
69 lines
1.5 KiB
Verilog
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module catcap_ddr_cmos
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(input data_clk,
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input reset,
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input mimo,
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input rx_frame,
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input [11:0] rx_d,
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output rx_clk, output rx_strobe,
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output reg [11:0] i0, output reg [11:0] q0,
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output reg [11:0] i1, output reg [11:0] q1);
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//IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
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//clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
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wire [11:0] i,q;
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wire frame_0, frame_1;
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genvar z;
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generate
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for(z = 0; z < 12; z = z + 1)
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begin : gen_pins
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IDDR2 #(.DDR_ALIGNMENT("C0")) iddr2
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(.Q0(q[z]), .Q1(i[z]), .C0(data_clk), .C1(~data_clk),
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.CE(1'b1), .D(rx_d[z]), .R(1'b0), .S(1'b0));
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end
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endgenerate
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IDDR2 #(.DDR_ALIGNMENT("C0")) iddr2_frame
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(.Q0(frame_0), .Q1(frame_1), .C0(data_clk), .C1(~data_clk),
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.CE(1'b1), .D(rx_frame), .R(1'b0), .S(1'b0));
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reg frame_d1, frame_d2;
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always @(posedge data_clk)
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if(reset)
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{ frame_d2, frame_d1 } <= 0;
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else if(~mimo)
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{ frame_d2, frame_d1 } <= { frame_1, 1'b0 };
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else
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{ frame_d2, frame_d1 } <= { frame_d1, frame_1 };
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assign rx_strobe = frame_d2;
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reg [11:0] i_del, q_del;
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always @(posedge data_clk)
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if(mimo)
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if(frame_0)
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begin
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i_del <= i;
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q_del <= q;
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end
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else
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begin
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i1 <= i;
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q1 <= q;
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i0 <= i_del;
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q0 <= q_del;
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end
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else
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begin
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i0 <= i;
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q0 <= q;
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i1 <= i;
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q1 <= q;
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end
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assign rx_clk = data_clk;
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endmodule // catcap_ddr_cmos
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