106 lines
3.4 KiB
VHDL
106 lines
3.4 KiB
VHDL
-- ZPU
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--
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-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
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--
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-- The FreeBSD license
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- The views and conclusions contained in the software and documentation
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-- are those of the authors and should not be interpreted as representing
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-- official policies, either expressed or implied, of the ZPU Project.
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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library work;
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use work.zpu_top_pkg.all;
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use work.wishbone_pkg.all;
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use work.zpupkg.all;
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use work.zpu_config.all;
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entity zpu_system is
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generic(
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simulate : boolean := false);
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port ( areset : in std_logic;
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cpu_clk : in std_logic;
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-- ZPU Control signals
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enable : in std_logic;
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interrupt : in std_logic;
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zpu_status : out std_logic_vector(63 downto 0);
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-- wishbone interfaces
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zpu_wb_i : in wishbone_bus_out;
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zpu_wb_o : out wishbone_bus_in);
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end zpu_system;
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architecture behave of zpu_system is
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signal mem_req : std_logic;
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signal mem_we : std_logic;
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signal mem_ack : std_logic;
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signal mem_read : std_logic_vector(wordSize-1 downto 0);
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signal mem_write : std_logic_vector(wordSize-1 downto 0);
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signal out_mem_addr : std_logic_vector(maxAddrBitIncIO downto 0);
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signal mem_writeMask : std_logic_vector(wordBytes-1 downto 0);
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begin
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my_zpu_core:
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zpu_core port map (
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clk => cpu_clk,
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areset => areset,
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enable => enable,
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mem_req => mem_req,
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mem_we => mem_we,
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mem_ack => mem_ack,
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mem_read => mem_read,
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mem_write => mem_write,
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out_mem_addr => out_mem_addr,
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mem_writeMask => mem_writeMask,
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interrupt => interrupt,
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zpu_status => zpu_status,
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break => open);
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my_zpu_wb_bridge:
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zpu_wb_bridge port map (
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clk => cpu_clk,
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areset => areset,
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mem_req => mem_req,
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mem_we => mem_we,
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mem_ack => mem_ack,
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mem_read => mem_read,
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mem_write => mem_write,
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out_mem_addr => out_mem_addr,
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mem_writeMask => mem_writeMask,
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zpu_wb_i => zpu_wb_i,
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zpu_wb_o => zpu_wb_o);
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end behave;
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