87 lines
2.9 KiB
VHDL
87 lines
2.9 KiB
VHDL
-- ZPU
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--
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-- Copyright 2004-2008 oharboe - Øyvind Harboe - oyvind.harboe@zylin.com
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--
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-- The FreeBSD license
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-- The views and conclusions contained in the software and documentation
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-- are those of the authors and should not be interpreted as representing
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-- official policies, either expressed or implied, of the ZPU Project.
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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package wishbone_pkg is
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type wishbone_bus_in is record
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adr : std_logic_vector(15 downto 0);
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sel : std_logic_vector(3 downto 0);
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we : std_logic;
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dat : std_logic_vector(31 downto 0); -- Note! Data written with 'we'
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cyc : std_logic;
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stb : std_logic;
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end record;
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type wishbone_bus_out is record
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dat : std_logic_vector(31 downto 0);
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ack : std_logic;
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end record;
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type wishbone_bus is record
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insig : wishbone_bus_in;
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outsig : wishbone_bus_out;
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end record;
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component atomic32_access is
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port ( cpu_clk : in std_logic;
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areset : in std_logic;
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-- Wishbone from CPU interface
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wb_16_i : in wishbone_bus_in;
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wb_16_o : out wishbone_bus_out;
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-- Wishbone to FPGA registers and ethernet core
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wb_32_i : in wishbone_bus_out;
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wb_32_o : out wishbone_bus_in);
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end component;
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component eth_access_corr is
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port ( cpu_clk : in std_logic;
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areset : in std_logic;
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-- Wishbone from Wishbone MUX
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eth_raw_o : out wishbone_bus_out;
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eth_raw_i : in wishbone_bus_in;
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-- Wishbone ethernet core
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eth_slave_i : in wishbone_bus_out;
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eth_slave_o : out wishbone_bus_in);
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end component;
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end wishbone_pkg;
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