53 lines
1.7 KiB
Verilog
53 lines
1.7 KiB
Verilog
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module tx_responder
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#(parameter BASE = 0)
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(input clk, input reset, input clear,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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input ack_or_error, input packet_consumed,
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input [11:0] seqnum,
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input [63:0] error_code,
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input [31:0] sid,
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input [63:0] vita_time,
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output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
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reg [11:0] seqnum_int;
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always @(posedge clk)
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if(packet_consumed)
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seqnum_int <= seqnum;
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wire trigger_fc, trigger_ctxt;
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wire [95:0] msg_data = { sid[15:0], sid[31:16], (ack_or_error ? error_code : {32'h0,20'h0,seqnum_int}) };
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wire [95:0] ctxt_data;
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reg [11:0] reply_seqnum;
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wire done;
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always @(posedge clk)
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if(reset | clear)
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reply_seqnum <= 12'd0;
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else if(done)
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reply_seqnum <= reply_seqnum + 12'd1;
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trigger_context_pkt #(.BASE(BASE)) trig
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(.clk(clk), .reset(reset), .clear(clear),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.packet_consumed(packet_consumed), .trigger(trigger_fc));
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axi_fifo_short #(.WIDTH(64+32)) ack_queue
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(.clk(clk), .reset(reset), .clear(clear),
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.i_tdata(msg_data), .i_tvalid(ack_or_error | trigger_fc), .i_tready(),
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.o_tdata(ctxt_data), .o_tvalid(trigger_ctxt), .o_tready(done),
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.space(), .occupied());
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context_packet_gen ack_err_gen
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(.clk(clk), .reset(reset), .clear(clear),
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.trigger(trigger_ctxt), .seqnum(reply_seqnum), .sid(ctxt_data[95:64]),
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.body(ctxt_data[63:0]), .vita_time(vita_time),
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.done(done),
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.o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready));
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endmodule // tx_responder
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