136 lines
3.1 KiB
Verilog
136 lines
3.1 KiB
Verilog
`timescale 1ns/1ps
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module new_rx_tb();
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reg clk = 0;
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reg reset = 1;
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always #10 clk = ~clk;
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initial $dumpfile("new_rx_tb.vcd");
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initial $dumpvars(0,new_rx_tb);
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initial
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begin
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#1000 reset = 0;
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#30000;
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$finish;
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end
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reg [7:0] set_addr;
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reg [31:0] set_data;
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reg set_stb = 1'b0;
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reg [63:0] vita_time;
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reg [31:0] sample;
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reg strobe;
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wire run, full;
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wire [63:0] err_tdata;
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wire err_tlast, err_tvalid, err_tready;
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wire [63:0] o_tdata;
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wire o_tlast, o_tvalid;
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reg o_tready;
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task send_command;
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input [63:0] send_time;
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input send_at;
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input chain;
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input reload;
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input stop;
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input [31:0] len;
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begin
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set_stb <= 1;
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set_addr <= 0;
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set_data <= { send_at, chain, reload, stop, len };
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@(posedge clk);
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set_stb <= 1;
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set_addr <= 1;
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set_data <= send_time[63:32];
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@(posedge clk);
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set_stb <= 1;
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set_addr <= 2;
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set_data <= send_time[31:0];
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@(posedge clk);
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set_stb <= 0;
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@(posedge clk);
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end
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endtask // send_command
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initial
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begin
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o_tready <= 0;
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while(reset)
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@(posedge clk);
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set_stb <= 1; // Set Max Length of Packet
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set_addr <= 8;
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set_data <= 18;
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@(posedge clk);
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set_stb <= 1; // Set SID
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set_addr <= 9;
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set_data <= 32'hF00D_1234;
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@(posedge clk);
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send_command(64'h100/*time*/, 1/*send at*/, 0/*chain*/, 0/*reload*/,0/*stop*/,150/*len*/);
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send_command(64'h200/*time*/, 1/*send at*/, 0/*chain*/, 0/*reload*/,0/*stop*/,4/*len*/);
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//send_command(64'h100/*time*/, 1/*send at*/, 0/*chain*/, 0/*reload*/,0/*stop*/,5/*len*/);
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#8000;
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o_tready <= 1;
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end // initial begin
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always @(posedge clk)
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if(reset)
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vita_time <= 0;
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else
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vita_time <= vita_time + 1;
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new_rx_control #(.BASE(0)) rx_control
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(.clk(clk), .reset(reset), .clear(1'b0),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.vita_time(vita_time),
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.run(run), .eob(eob), .strobe(strobe), .full(full),
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.err_tdata(err_tdata), .err_tlast(err_tlast), .err_tvalid(err_tvalid), .err_tready(err_tready),
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.debug());
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new_rx_framer #(.BASE(8)) rx_framer
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(.clk(clk), .reset(reset), .clear(1'b0),
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.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
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.vita_time(vita_time),
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.strobe(strobe), .sample(sample), .run(run), .eob(eob), .full(full),
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.o_tdata(o_tdata), .o_tlast(o_tlast), .o_tvalid(o_tvalid), .o_tready(o_tready)
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);
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always @*
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strobe <= run;
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/*
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always @(posedge clk)
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if(reset)
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sample <= 0;
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else if(run)
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sample <= sample + 1;
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*/
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always @* sample <= vita_time[31:0];
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always @(posedge clk)
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if(o_tvalid & o_tready)
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if(o_tlast)
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$display("%x\tLAST\n",o_tdata);
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else
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$display("%x",o_tdata);
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assign err_tready = 1;
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always @(posedge clk)
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if(err_tvalid & err_tready)
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if(err_tlast)
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$display("\t\t\t\tERR LAST \t%x",err_tdata);
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else
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$display("\t\t\t\tERR\t\t%x",err_tdata);
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endmodule // new_rx_tb
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