254 lines
7.9 KiB
Verilog
254 lines
7.9 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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// HALT brings RX to an idle state as quickly as possible if RX is running
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// without running the risk of leaving a packet fragment in downstream FIFO's.
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// HALT also flushes all remaining pending commands in the commmand FIFO.
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// Unlike STOP, HALT doesn't ever create an ERROR packet.
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module new_rx_control
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#(parameter BASE=0)
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(input clk, input reset, input clear,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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input [63:0] vita_time,
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// DDC connections
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output run, output eob,
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input strobe, input full,
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input [11:0] seqnum,
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input [31:0] sid,
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output [63:0] err_tdata, output err_tlast, output err_tvalid, input err_tready,
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output [31:0] debug
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);
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wire [31:0] command_i;
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wire [63:0] time_i;
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wire store_command;
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wire send_imm, chain, reload, stop;
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wire [27:0] numlines;
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wire [63:0] rcvtime;
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wire now, early, late;
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wire command_valid;
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reg command_ready;
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reg chain_sav, reload_sav;
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reg clear_halt;
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reg halt;
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wire set_halt;
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reg [63:0] err_tdata_int;
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wire err_tlast_int;
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wire err_tvalid_int;
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wire err_tready_int;
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setting_reg #(.my_addr(BASE)) sr_cmd
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(command_i),.changed());
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setting_reg #(.my_addr(BASE+1)) sr_time_h
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(time_i[63:32]),.changed());
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setting_reg #(.my_addr(BASE+2)) sr_time_l
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(time_i[31:0]),.changed(store_command));
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setting_reg #(.my_addr(BASE+3)) sr_rx_halt
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(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(),.changed(set_halt));
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always @(posedge clk)
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if (reset | clear | clear_halt)
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halt <= 1'b0;
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else
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halt <= set_halt;
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axi_fifo_short #(.WIDTH(96)) commandfifo
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(.clk(clk),.reset(reset),.clear(clear | clear_halt),
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.i_tdata({command_i,time_i}), .i_tvalid(store_command), .i_tready(),
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.o_tdata({send_imm,chain,reload,stop,numlines,rcvtime}),
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.o_tvalid(command_valid), .o_tready(command_ready),
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.occupied(), .space() );
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time_compare
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time_compare (.clk(clk), .reset(reset), .time_now(vita_time), .trigger_time(rcvtime), .now(now), .early(early), .late(late));
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localparam IBS_IDLE = 0;
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localparam IBS_RUNNING = 1;
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localparam IBS_OVERRUN = 2;
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localparam IBS_OVR_TIME = 3;
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localparam IBS_OVR_DATA = 4;
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localparam IBS_BROKENCHAIN = 5;
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localparam IBS_BRK_TIME = 6;
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localparam IBS_BRK_DATA = 7;
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localparam IBS_LATECMD = 8;
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localparam IBS_LATE_TIME = 9;
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localparam IBS_LATE_DATA = 10;
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localparam IBS_ZEROLEN = 11;
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localparam IBS_ZERO_TIME = 12;
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localparam IBS_ZERO_DATA = 13;
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reg [3:0] ibs_state;
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reg [27:0] lines_left, repeat_lines;
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always @(posedge clk)
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if(reset | clear)
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begin
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ibs_state <= IBS_IDLE;
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chain_sav <= 1'b0;
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reload_sav <= 1'b0;
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clear_halt <= 1'b0;
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end
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else
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case (ibs_state)
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IBS_IDLE : begin
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clear_halt <= 1'b0; // Incase we got here through a HALT.
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if (command_valid)
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// There is a valid command to pop from FIFO.
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if (stop) begin
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// Stop bit set in this command, go idle.
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ibs_state <= IBS_IDLE;//IBS_ZEROLEN;
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end else if (late & ~send_imm) begin
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// Got this command later than its execution time.
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ibs_state <= IBS_LATECMD;
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end else if (now | send_imm) begin
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// Either its time to run this command or it should run immediately without a time.
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ibs_state <= IBS_RUNNING;
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lines_left <= numlines;
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repeat_lines <= numlines;
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chain_sav <= chain;
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reload_sav <= reload;
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end
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end // case: IBS_IDLE
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IBS_RUNNING : begin
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if (strobe) begin
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if (full) begin
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// Framing FIFO is full and we have just overrun.
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ibs_state <= IBS_OVERRUN;
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end else if (lines_left == 1) begin
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// Provide Halt mechanism used to bring RX into known IDLE state
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// at re-initialization.
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if (halt) begin
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ibs_state <= IBS_IDLE;
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clear_halt <= 1'b1;
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end else if (chain_sav) begin
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// If chain_sav is true then execute the next command now this one finished.
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if (command_valid) begin
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lines_left <= numlines;
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repeat_lines <= numlines;
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chain_sav <= chain;
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reload_sav <= reload;
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// If the new command includes stop then go idle.
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if (stop) begin
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ibs_state <= IBS_IDLE;
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end
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end else if (reload_sav) begin
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// There is no new command to pop from FIFO so re-run previous command.
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lines_left <= repeat_lines;
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end else begin
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// Chain has been broken, no commands left in FIFO and reload not set.
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ibs_state <= IBS_BROKENCHAIN;
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end
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end else begin // if (chain_sav)
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// Chain is not true, so don't look for new command, instead go idle.
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ibs_state <= IBS_IDLE;
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end
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end else begin // if (lines_left == 1)
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// Still counting down lines in current command.
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lines_left <= lines_left - 28'd1;
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end
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end // if (strobe)
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end // case: IBS_RUNNING
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IBS_OVERRUN: if(err_tready_int) ibs_state <= IBS_OVR_TIME;
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IBS_OVR_TIME: if(err_tready_int) ibs_state <= IBS_OVR_DATA;
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IBS_OVR_DATA: if(err_tready_int) ibs_state <= IBS_IDLE;
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IBS_BROKENCHAIN: if(err_tready_int) ibs_state <= IBS_BRK_TIME;
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IBS_BRK_TIME: if(err_tready_int) ibs_state <= IBS_BRK_DATA;
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IBS_BRK_DATA: if(err_tready_int) ibs_state <= IBS_IDLE;
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IBS_LATECMD: if(err_tready_int) ibs_state <= IBS_LATE_TIME;
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IBS_LATE_TIME: if(err_tready_int) ibs_state <= IBS_LATE_DATA;
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IBS_LATE_DATA: if(err_tready_int) ibs_state <= IBS_IDLE;
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IBS_ZEROLEN: if(err_tready_int) ibs_state <= IBS_ZERO_TIME;
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IBS_ZERO_TIME: if(err_tready_int) ibs_state <= IBS_ZERO_DATA;
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IBS_ZERO_DATA: if(err_tready_int) ibs_state <= IBS_IDLE;
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default: ibs_state <= IBS_IDLE;
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endcase // case (ibs_state)
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always @*
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case(ibs_state)
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IBS_IDLE : command_ready <= stop | late | now | send_imm;
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IBS_RUNNING : command_ready <= strobe & (lines_left == 1) & chain_sav;
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default : command_ready <= 1'b0;
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endcase // case (ibs_state)
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assign run = (ibs_state == IBS_RUNNING);
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assign eob = strobe && (lines_left == 1) && ( !chain_sav || (command_valid && stop) || (!command_valid && !reload_sav) || halt);
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always @*
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case (ibs_state)
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IBS_OVERRUN : err_tdata_int <= { 4'hA, seqnum, 16'd24, sid };
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IBS_OVR_TIME : err_tdata_int <= vita_time;
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IBS_OVR_DATA : err_tdata_int <= {32'h8, 32'b0};
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IBS_BROKENCHAIN : err_tdata_int <= { 4'hA, seqnum, 16'd24, sid };
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IBS_BRK_TIME : err_tdata_int <= vita_time;
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IBS_BRK_DATA : err_tdata_int <= {32'h4, 32'b0};
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IBS_LATECMD : err_tdata_int <= { 4'hA, seqnum, 16'd24, sid };
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IBS_LATE_TIME : err_tdata_int <= vita_time;
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IBS_LATE_DATA : err_tdata_int <= {32'h2, 32'b0};
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IBS_ZEROLEN : err_tdata_int <= { 4'hA, seqnum, 16'd24, sid };
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IBS_ZERO_TIME : err_tdata_int <= vita_time;
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IBS_ZERO_DATA : err_tdata_int <= {32'hd, 32'b0};
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default : err_tdata_int <= {32'he, 32'b0};
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endcase // case (ibs_state)
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assign err_tlast_int = (ibs_state == IBS_OVR_DATA)
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| (ibs_state == IBS_BRK_DATA)
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| (ibs_state == IBS_LATE_DATA)
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| (ibs_state == IBS_ZERO_DATA);
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assign err_tvalid_int = ibs_state >= IBS_OVERRUN;
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assign debug[3:0] = ibs_state;
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assign debug[9:4] = {send_imm,chain,reload,stop, command_valid, command_ready};
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axi_fifo_short #(.WIDTH(65)) output_fifo
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(
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.clk(clk), .reset(reset), .clear(clear),
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.i_tdata({err_tlast_int,err_tdata_int}), .i_tvalid(err_tvalid_int), .i_tready(err_tready_int),
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.o_tdata({err_tlast,err_tdata}), .o_tvalid(err_tvalid), .o_tready(err_tready),
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.space(), .occupied()
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);
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endmodule // new_rx_control
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