108 lines
3.6 KiB
Verilog
108 lines
3.6 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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`timescale 500ps/1ps
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module pcie_iop2_msg_arbiter_tb();
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reg clk = 0;
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reg reset = 1;
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always #10 clk = ~clk;
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initial begin
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#100 reset = 0;
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#200000;
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$finish;
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end
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function [63:0] iop2_msg_write;
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input [19:0] address;
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input [31:0] data;
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input half_wd;
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begin
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// {rd_response, wr_request, rd_request, half_word, 8'h00, address, data};
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iop2_msg_write = {1'b0, 1'b1, 1'b0, half_wd, 8'h00, address, data};
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end
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endfunction // iop2_msg_write
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function [63:0] iop2_msg_read;
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input [19:0] address;
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input half_wd;
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begin
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// {rd_response, wr_request, rd_request, half_word, 8'h00, address, data};
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iop2_msg_read = {1'b0, 1'b0, 1'b1, half_wd, 8'h00, address, 32'h0};
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end
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endfunction // iop2_msg_read
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reg [63:0] msgi_tdata;
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wire [63:0] msgo_tdata;
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wire msgo_tvalid, msgi_tready;
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reg msgo_tready, msgi_tvalid;
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wire [63:0] basic_regi_tdata, zpu_regi_tdata;
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wire basic_regi_tvalid, zpu_regi_tvalid;
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reg basic_regi_tready, zpu_regi_tready;
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reg [63:0] basic_rego_tdata, zpu_rego_tdata;
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reg basic_rego_tvalid, zpu_rego_tvalid;
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wire basic_rego_tready, zpu_rego_tready;
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initial begin
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//@TODO: Make this a self-checking TB
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while (reset) @(posedge clk);
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msgo_tready <= 1;
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basic_regi_tready <= 1;
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@(posedge clk);
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msgi_tdata <= iop2_msg_write(20'h0, 32'hDEAD, 0);
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msgi_tvalid <= 1;
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while (~msgi_tready) @(posedge clk);
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msgi_tvalid <= 0;
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@(posedge clk);
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msgi_tdata <= iop2_msg_read(20'h00000, 0);
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msgi_tvalid <= 1;
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while (~msgi_tready) @(posedge clk);
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msgi_tvalid <= 0;
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@(posedge clk);
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zpu_rego_tdata <= {1, 31'h0, 32'h12345678};
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zpu_rego_tvalid <= 1;
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while (~zpu_rego_tready) @(posedge clk);
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zpu_rego_tvalid <= 0;
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end // initial begin
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pcie_iop2_msg_arbiter #(
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.E0_ADDR(20'h00000), .E0_MASK(20'hFFF00), //0x00000 - 0x000FF: Basic PCIe registers
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.E1_ADDR(20'h00100), .E1_MASK(20'hFFF00), //0x00100 - 0x001FF: PCIe router registers
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.E2_ADDR(20'h00200), .E2_MASK(20'hFFE00), //0x00200 - 0x003FF: DMA stream registers
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.E3_ADDR(20'h40000), .E3_MASK(20'hC0000) //0x40000 - 0x7FFFF: Client address space
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) iop2_msg_arbiter (
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.clk(clk), .reset(reset),
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//Master
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.regi_tdata(msgi_tdata), .regi_tvalid(msgi_tvalid), .regi_tready(msgi_tready),
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.rego_tdata(msgo_tdata), .rego_tvalid(msgo_tvalid), .rego_tready(msgo_tready),
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//Endpoint 0
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.e0_regi_tdata(basic_regi_tdata), .e0_regi_tvalid(basic_regi_tvalid), .e0_regi_tready(basic_regi_tready),
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.e0_rego_tdata(basic_rego_tdata), .e0_rego_tvalid(basic_rego_tvalid), .e0_rego_tready(basic_rego_tready),
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//Endpoint 1
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.e1_regi_tdata(), .e1_regi_tvalid(), .e1_regi_tready(1'b1),
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.e1_rego_tdata(64'h0), .e1_rego_tvalid(1'b0), .e1_rego_tready(),
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//Endpoint 2
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.e2_regi_tdata(), .e2_regi_tvalid(), .e2_regi_tready(1'b1),
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.e2_rego_tdata(64'h0), .e2_rego_tvalid(1'b0), .e2_rego_tready(),
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//Endpoint 3
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.e3_regi_tdata(zpu_regi_tdata), .e3_regi_tvalid(zpu_regi_tvalid), .e3_regi_tready(zpu_regi_tready),
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.e3_rego_tdata(zpu_rego_tdata), .e3_rego_tvalid(zpu_rego_tvalid), .e3_rego_tready(zpu_rego_tready)
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);
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endmodule
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