50 lines
1.4 KiB
Verilog
50 lines
1.4 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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//Message format:
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// msg[63]: Completion {1 -> Read Completion, 0 -> Transaction Request}
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// msg[62]: Write request*
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// msg[61]: Read request*
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// msg[60]: Half word {1 -> 16-bit transaction, 0 -> 32-bit transaction}*
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// msg[59:52]: Reserved
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// msg[51:32]: Address*
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// msg[31:0]: Data
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//
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// * Field only valid when the word is a transaction request.
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module ioport2_msg_decode(
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input [63:0] message,
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output rd_response,
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output wr_request,
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output rd_request,
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output half_word,
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output [19:0] address,
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output [31:0] data,
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output [31:0] control
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);
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assign rd_response = message[63];
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assign wr_request = message[62];
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assign rd_request = message[61];
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assign half_word = message[60];
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assign address = message[51:32];
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assign data = message[31:0];
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assign control = message[63:32];
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endmodule
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module ioport2_msg_encode(
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input rd_response,
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input wr_request,
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input rd_request,
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input half_word,
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input [19:0] address,
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input [31:0] data,
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output [31:0] control,
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output [63:0] message
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);
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assign control = rd_response ? {rd_response, 31'h0} : {rd_response, wr_request, rd_request, half_word, 8'h00, address};
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assign message = {control, data};
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endmodule
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