24 lines
774 B
Verilog
24 lines
774 B
Verilog
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module round_sd
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#(parameter WIDTH_IN=18,
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parameter WIDTH_OUT=16,
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parameter DISABLE_SD=0)
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(input clk, input reset,
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input [WIDTH_IN-1:0] in, input strobe_in,
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output [WIDTH_OUT-1:0] out, output strobe_out);
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localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1;
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wire [ERR_WIDTH-1:0] err;
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wire [WIDTH_IN-1:0] err_ext, sum;
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sign_extend #(.bits_in(ERR_WIDTH),.bits_out(WIDTH_IN)) ext_err (.in(err), .out(err_ext));
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add2_and_clip_reg #(.WIDTH(WIDTH_IN)) add2_and_clip_reg
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(.clk(clk), .rst(reset), .in1(in), .in2((DISABLE_SD == 0) ? err_ext : 0), .strobe_in(strobe_in), .sum(sum), .strobe_out(strobe_out));
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round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out), .err(err));
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endmodule // round_sd
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