82 lines
1.4 KiB
Verilog
82 lines
1.4 KiB
Verilog
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module serial_to_settings_tb();
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reg clk;
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reg reset;
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wire scl;
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wire sda;
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wire set_stb;
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wire [7:0] set_addr;
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wire [31:0] set_data;
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//
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// These registers optionaly used
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// to drive nets through procedural assignments in test bench.
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// These drivers default to tri-stated.
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//
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reg scl_r;
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reg sda_r;
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assign scl = scl_r;
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assign sda = sda_r;
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initial
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begin
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scl_r <= 1'bz;
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sda_r <= 1'bz;
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end
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serial_to_settings serial_to_settings_i
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(
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.clk(clk),
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.reset(reset),
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// Serial signals (async)
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.scl(scl),
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.sda(sda),
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// Settngs bus out
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.set_stb(set_stb),
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.set_addr(set_addr),
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.set_data(set_data)
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);
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// Nasty HAck to convert settings to wishbone crudely.
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reg wb_stb;
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wire wb_ack_o;
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always @(posedge clk)
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if (reset)
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wb_stb <= 0;
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else
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wb_stb <= set_stb ? 1 : ((wb_ack_o) ? 0 : wb_stb);
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simple_uart debug_uart
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(
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.clk_i(clk),
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.rst_i(reset),
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.we_i(wb_stb),
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.stb_i(wb_stb),
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.cyc_i(wb_stb),
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.ack_o(wb_ack_o),
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.adr_i(set_addr[2:0]),
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.dat_i(set_data[31:0]),
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.dat_o(),
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.rx_int_o(),
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.tx_int_o(),
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.tx_o(txd),
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.rx_i(rxd),
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.baud_o()
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);
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//
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// Bring in a simulation script here
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//
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`include "simulation_script.v"
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endmodule |