Wade Fife
0c6f2627a5
Fixes various synthesis/simulation warnings that were being generated due to incorrectly sized constants. Original-commit: 00f683c91486647f1711eb4c0b0a917078d29652
123 lines
4.4 KiB
Verilog
123 lines
4.4 KiB
Verilog
//
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// Copyright 2018 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: chdr_xb_routing_table
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// Description:
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// A routing table for the CHDR crossbar. This table is designed
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// to be shared between all ports. It has an AXI-Stream lookup
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// interface and a ctrlport (reduced) configuration interface.
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module chdr_xb_routing_table #(
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parameter SIZE = 6,
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parameter NPORTS = 4,
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parameter EXT_INS_PORT_EN = 1
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) (
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// Clocks and resets
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input wire clk,
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input wire reset,
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// Insertion Interface (for XB ports)
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input wire [NPORTS-1:0] port_req_wr,
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input wire [(16*NPORTS)-1:0] port_req_addr,
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input wire [(32*NPORTS)-1:0] port_req_data,
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output wire [NPORTS-1:0] port_resp_ack,
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// Insertion Interface (External)
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input wire ext_req_wr,
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input wire [15:0] ext_req_addr,
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input wire [31:0] ext_req_data,
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output wire ext_resp_ack,
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// Find Interface
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input wire [(16*NPORTS)-1:0] axis_find_tdata,
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input wire [NPORTS-1:0] axis_find_tvalid,
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output wire [NPORTS-1:0] axis_find_tready,
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// Result Interface (for Find)
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output wire [($clog2(NPORTS)*NPORTS)-1:0] axis_result_tdata,
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output wire [NPORTS-1:0] axis_result_tkeep,
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output wire [NPORTS-1:0] axis_result_tvalid,
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input wire [NPORTS-1:0] axis_result_tready
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);
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localparam NPORTS_W = $clog2(NPORTS);
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localparam CFG_W = NPORTS_W + 16;
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localparam CFG_PORTS = NPORTS + EXT_INS_PORT_EN;
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// CAM-based lookup table
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wire [15:0] insert_tdest;
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wire [NPORTS_W-1:0] insert_tdata;
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wire insert_tvalid;
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wire insert_tready;
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axis_muxed_kv_map #(
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.KEY_WIDTH(16), .VAL_WIDTH(NPORTS_W),
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.SIZE(SIZE), .NUM_PORTS(NPORTS)
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) kv_map_i (
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.clk (clk ),
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.reset (reset ),
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.axis_insert_tdata (insert_tdata ),
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.axis_insert_tdest (insert_tdest ),
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.axis_insert_tvalid(insert_tvalid ),
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.axis_insert_tready(insert_tready ),
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.axis_find_tdata (axis_find_tdata ),
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.axis_find_tvalid (axis_find_tvalid ),
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.axis_find_tready (axis_find_tready ),
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.axis_result_tdata (axis_result_tdata ),
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.axis_result_tkeep (axis_result_tkeep ),
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.axis_result_tvalid(axis_result_tvalid),
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.axis_result_tready(axis_result_tready)
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);
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// Logic to convert from ctrlport to AXI-Stream
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wire ins_req_wr [0:CFG_PORTS-1];
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wire [15:0] ins_req_addr[0:CFG_PORTS-1];
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wire [NPORTS_W-1:0] ins_req_data[0:CFG_PORTS-1];
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wire ins_resp_ack[0:CFG_PORTS-1];
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reg [(CFG_PORTS*CFG_W)-1:0] cfg_tdata;
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reg [CFG_PORTS-1:0] cfg_tvalid = {CFG_PORTS{1'b0}};
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wire [CFG_PORTS-1:0] cfg_tready;
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genvar i;
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generate for (i = 0; i < CFG_PORTS; i=i+1) begin
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assign ins_req_wr [i] = (i < NPORTS) ? port_req_wr[i] : ext_req_wr;
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assign ins_req_addr[i] = (i < NPORTS) ? port_req_addr[i*16 +: 16] : ext_req_addr;
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assign ins_req_data[i] = (i < NPORTS) ? port_req_data[i*32 +: NPORTS_W] : ext_req_data[NPORTS_W-1:0];
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if (i < NPORTS)
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assign port_resp_ack[i] = ins_resp_ack[i];
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else
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assign ext_resp_ack = ins_resp_ack[i];
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always @(posedge clk) begin
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if (reset) begin
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cfg_tvalid[i] <= 1'b0;
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end else begin
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if (~cfg_tvalid[i]) begin
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if (ins_req_wr[i]) begin
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cfg_tvalid[i] <= 1'b1;
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cfg_tdata[(CFG_W*i) +: CFG_W] <= {ins_req_data[i], ins_req_addr[i]};
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end
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end else begin
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cfg_tvalid[i] <= ~cfg_tready[i];
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end
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end
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end
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assign ins_resp_ack[i] = cfg_tvalid[i] & cfg_tready[i];
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end endgenerate
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// Multiplexer between XB ports and external cfg
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axi_mux #(
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.WIDTH(CFG_W), .SIZE(CFG_PORTS),
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.PRE_FIFO_SIZE(0), .POST_FIFO_SIZE(1)
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) rtcfg_mux_i (
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.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata(cfg_tdata), .i_tlast({CFG_PORTS{1'b1}}),
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.i_tvalid(cfg_tvalid), .i_tready(cfg_tready),
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.o_tdata({insert_tdata, insert_tdest}), .o_tlast(),
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.o_tvalid(insert_tvalid), .o_tready(insert_tready)
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);
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endmodule
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