adf6f576c6
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
131 lines
4.0 KiB
Verilog
131 lines
4.0 KiB
Verilog
//
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_clk_crossing_derived
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//
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// Description:
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// Performs a simplified clk crossing for a ctrlport interface.
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// i_clk must be derived from o_clk by an integer multiplier and
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// originate from the same PLL. This ensures the clock crossing
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// can be achieved by using simple registers, as STA will be able
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// to meet setup and hold requirements on them.
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//
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`default_nettype none
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module ctrlport_clk_crossing_derived (
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// Clocks
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input wire i_clk,
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input wire o_clk,
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// Request (domain: i_clk)
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input wire i_ctrlport_rst,
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input wire i_ctrlport_req_wr,
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input wire i_ctrlport_req_rd,
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input wire [19:0] i_ctrlport_req_addr,
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input wire [31:0] i_ctrlport_req_data,
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// Response (domain: i_clk)
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output wire i_ctrlport_resp_ack,
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output reg [ 1:0] i_ctrlport_resp_status,
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output reg [31:0] i_ctrlport_resp_data,
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// Request (domain: o_clk)
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output reg o_ctrlport_rst,
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output reg o_ctrlport_req_wr,
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output reg o_ctrlport_req_rd,
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output reg [19:0] o_ctrlport_req_addr,
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output reg [31:0] o_ctrlport_req_data,
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// Response (domain: o_clk)
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input wire o_ctrlport_resp_ack,
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input wire [ 1:0] o_ctrlport_resp_status,
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input wire [31:0] o_ctrlport_resp_data
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);
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// holding read and write flags for multiple i_clk cycles
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reg ctrlport_req_wr_hold = 1'b0;
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reg ctrlport_req_rd_hold = 1'b0;
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reg ctrlport_req_rd_fall = 1'b0;
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reg ctrlport_req_wr_fall = 1'b0;
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reg [31:0] ctrlport_resp_data_fall = 32'b0;
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reg [ 1:0] ctrlport_resp_status_fall = 2'b0;
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reg ctrlport_resp_ack_fall = 1'b0;
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// Retime signals to falling edge of i_clk. By sampling on the falling edge of
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// i_clk, we provide (nominally) half a i_clk period of hold, while
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// reducing setup time by half. The late arrival of i_clk adds back some
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// of the lost setup margin.
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always @(negedge i_clk) begin
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ctrlport_req_rd_fall <= o_ctrlport_req_rd;
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ctrlport_req_wr_fall <= o_ctrlport_req_wr;
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ctrlport_resp_ack_fall <= o_ctrlport_resp_ack;
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ctrlport_resp_status_fall <= o_ctrlport_resp_status;
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ctrlport_resp_data_fall <= o_ctrlport_resp_data;
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end
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always @(posedge i_clk) begin
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if (ctrlport_req_wr_fall) begin
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ctrlport_req_wr_hold <= 1'b0;
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end else if (i_ctrlport_req_wr) begin
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ctrlport_req_wr_hold <= 1'b1;
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end
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if (ctrlport_req_rd_fall) begin
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ctrlport_req_rd_hold <= 1'b0;
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end else if (i_ctrlport_req_rd) begin
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ctrlport_req_rd_hold <= 1'b1;
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end
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// capture request address and data
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if (i_ctrlport_req_wr || i_ctrlport_req_rd) begin
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o_ctrlport_req_addr <= i_ctrlport_req_addr;
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o_ctrlport_req_data <= i_ctrlport_req_data;
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end
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end
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// capture extended flags in o_clk domain
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always @(posedge o_clk) begin
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o_ctrlport_req_wr <= ctrlport_req_wr_hold;
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o_ctrlport_req_rd <= ctrlport_req_rd_hold;
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end
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// search for rising edge in response
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reg [1:0] ctrlport_resp_ack_reg = 2'b0;
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always @(posedge i_clk) begin
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ctrlport_resp_ack_reg = {ctrlport_resp_ack_reg[0], ctrlport_resp_ack_fall};
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end
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assign i_ctrlport_resp_ack = ctrlport_resp_ack_reg[0] & ~ctrlport_resp_ack_reg[1];
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// capture response data
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always @(posedge i_clk) begin
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if (ctrlport_resp_ack_fall) begin
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i_ctrlport_resp_status <= ctrlport_resp_status_fall;
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i_ctrlport_resp_data <= ctrlport_resp_data_fall;
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end
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end
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// transfer reset
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reg ctrlport_rst_hold = 1'b0;
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reg ctrlport_rst_fall = 1'b0;
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always @(posedge i_clk) begin
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if (i_ctrlport_rst) begin
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ctrlport_rst_hold <= 1'b1;
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end else if (ctrlport_rst_fall) begin
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ctrlport_rst_hold <= 1'b0;
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end
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end
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always @(posedge o_clk) begin
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o_ctrlport_rst <= ctrlport_rst_hold;
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end
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always @(negedge i_clk) begin
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ctrlport_rst_fall <= o_ctrlport_rst;
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end
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endmodule
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`default_nettype wire
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