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Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade Fife
6b67702ad7
Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade FifeThe FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
168 lines
6.2 KiB
Plaintext
168 lines
6.2 KiB
Plaintext
<: set ComponentName [getComponentNameString] :>
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<: setOutputDirectory "./" :>
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<: setFileName [ttcl_add $ComponentName "_constr"] :>
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<: setFileExtension ".xdc" :>
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<: setFileProcessingOrder late :>
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<: set async_dest_req [getBooleanValue "ASYNC_CLK_DEST_REQ"] :>
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<: set async_req_src [getBooleanValue "ASYNC_CLK_REQ_SRC"] :>
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<: set async_src_dest [getBooleanValue "ASYNC_CLK_SRC_DEST"] :>
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set req_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
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set src_clk [get_clocks -of_objects [get_ports -quiet {fifo_wr_clk s_axis_aclk m_src_axi_aclk}]]
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set dest_clk [get_clocks -of_objects [get_ports -quiet {fifo_rd_clk m_axis_aclk m_dest_axi_aclk}]]
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<: if {$async_req_src || $async_src_dest || $async_dest_req} { :>
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set_property ASYNC_REG TRUE \
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[get_cells -quiet -hier *cdc_sync_stage1_reg*] \
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[get_cells -quiet -hier *cdc_sync_stage2_reg*]
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<: } :>
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<: if {$async_req_src} { :>
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set_max_delay -quiet -datapath_only \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_src_request_id* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $req_clk]
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set_false_path -quiet \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_status_src* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_control_src* && IS_SEQUENTIAL}]
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set_max_delay -quiet -datapath_only \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $req_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_src_req_fifo* && IS_SEQUENTIAL}] \
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-to $src_clk \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *eot_mem_reg* \
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-filter {NAME =~ *i_request_arb* && IS_SEQUENTIAL}] \
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-to $src_clk \
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[get_property -min PERIOD $src_clk]
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<: } :>
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<: if {$async_dest_req} { :>
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_req_response_id* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $dest_clk]
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set_false_path -quiet \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_status_dest* && IS_SEQUENTIAL}]
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set_false_path -quiet \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_control_dest* && IS_SEQUENTIAL}]
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set_max_delay -quiet -datapath_only \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $req_clk]
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_dest_req_fifo* && IS_SEQUENTIAL}] \
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-to $dest_clk \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $dest_clk]
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set_max_delay -quiet -datapath_only \
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-from $req_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $req_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
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-filter {NAME =~ *i_dest_response_fifo* && IS_SEQUENTIAL}] \
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-to $req_clk \
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[get_property -min PERIOD $req_clk]
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set_max_delay -quiet -datapath_only \
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-from [get_cells -quiet -hier *eot_mem_reg* \
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-filter {NAME =~ *i_request_arb* && IS_SEQUENTIAL}] \
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-to $dest_clk \
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[get_property -min PERIOD $dest_clk]
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<: } :>
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<: if {$async_src_dest} { :>
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_sync_dest_request_id* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $src_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_fifo/i_address_gray/i_waddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $src_clk]
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set_max_delay -quiet -datapath_only \
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-from $dest_clk \
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-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
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-filter {NAME =~ *i_fifo/i_address_gray/i_raddr_sync* && IS_SEQUENTIAL}] \
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[get_property -min PERIOD $dest_clk]
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# In SDP mode REGCEB should not be connected. When inferring the BRAM the tools
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# do it anyway. The signal is not used by the BRAM though. But since the clock
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# associated with REGCEB is the write clock and not the read clock we get a
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# timing problem. Mark the path as a false path so it is not timed.
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set_false_path -quiet \
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-to [get_pins -hier *ram_reg*/REGCEB -filter {NAME =~ *i_fifo*}]
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<: } :>
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# Reset signals
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set_false_path -quiet \
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-from $req_clk \
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-to [get_pins -quiet -hier *reset_shift_reg*/PRE]
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# Ignore timing for debug signals to register map
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set_false_path -quiet \
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-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
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-filter {name =~ *i_sync_src_request_id* && IS_SEQUENTIAL}] \
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-to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}]
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set_false_path -quiet \
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-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
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-filter {name =~ *i_sync_dest_request_id* && IS_SEQUENTIAL}] \
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-to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}]
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set_false_path -quiet \
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-from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && IS_SEQUENTIAL}] \
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-to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}]
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set_false_path -quiet \
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-from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && IS_SEQUENTIAL}] \
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-to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}]
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